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axi_logic_analyzer: Initial commit

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Adrian Costina 2017-01-31 16:23:56 +02:00
parent 9c975211da
commit 6604cc7322
6 changed files with 783 additions and 0 deletions
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library/axi_logic_analyzer/Makefile Normal file
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####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += axi_logic_analyzer.v
M_DEPS += axi_logic_analyzer_constr.xdc
M_DEPS += axi_logic_analyzer_ip.tcl
M_DEPS += axi_logic_analyzer_reg.v
M_DEPS += axi_logic_analyzer_trigger.v
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += component.xml
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.ip_user_files
M_FLIST += *.srcs
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
.PHONY: all clean clean-all
all: axi_logic_analyzer.xpr
clean:clean-all
clean-all:
rm -rf $(M_FLIST)
axi_logic_analyzer.xpr: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) axi_logic_analyzer_ip.tcl >> axi_logic_analyzer_ip.log 2>&1
####################################################################################
####################################################################################

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library/axi_logic_analyzer/axi_logic_analyzer.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_logic_analyzer (
input clk,
output clk_out,
input [15:0] data_i,
output reg [15:0] data_o,
output [15:0] data_t,
input [ 1:0] trigger_i,
output reg adc_valid,
output reg [15:0] adc_data,
input [15:0] dac_data,
input dac_valid,
output reg dac_read,
output trigger_out,
output [31:0] trigger_offset,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal registers
reg [15:0] data_m1 = 'd0;
reg [15:0] data_r = 'd0;
reg [ 1:0] trigger_m1 = 'd0;
reg [ 1:0] trigger_m2 = 'd0;
reg [31:0] downsampler_counter_la = 'd0;
reg [31:0] upsampler_counter_pg = 'd0;
reg sample_valid_la = 'd0;
reg adc_valid_d1 = 'd0;
reg adc_valid_d2 = 'd0;
// internal signals
wire up_clk;
wire up_rstn;
wire [13:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [13:0] up_raddr;
wire [31:0] divider_counter_la;
wire [31:0] divider_counter_pg;
wire [17:0] edge_detect_enable;
wire [17:0] rise_edge_enable;
wire [17:0] fall_edge_enable;
wire [17:0] low_level_enable;
wire [17:0] high_level_enable;
wire [31:0] trigger_delay;
wire trigger_logic; // 0-OR,1-AND,2-XOR,3-NOR,4-NAND,5-NXOR
wire clock_select;
wire [15:0] overwrite_enable;
wire [15:0] overwrite_data;
wire [15:0] io_selection;
wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
genvar i;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign trigger_offset = trigger_delay;
generate
for (i = 0 ; i < 16; i = i + 1) begin
assign data_t[i] = od_pp_n[i] ? io_selection[i] & !data_o[i] : io_selection[i];
always @(posedge clk) begin
data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
end
end
endgenerate
BUFGMUX BUFGMUX_inst (
.O (clk_out),
.I0 (data_i[0]),
.I1 (trigger_i[0]),
.S (clock_select));
// synchronization
always @(posedge clk) begin
data_m1 <= data_i;
trigger_m1 <= trigger_i;
trigger_m2 <= trigger_m1;
end
// transfer data at clock frequency
// if capture is enabled
always @(posedge clk) begin
adc_valid_d1 <= adc_valid_d2;
adc_valid <= adc_valid_d1;
if (sample_valid_la == 1'b1) begin
adc_data <= data_m1;
adc_valid_d2 <= 1'b1;
end else begin
adc_valid_d2 <= 1'b0;
end
end
// downsampler logic analyzer
always @(posedge clk) begin
if (reset == 1'b1) begin
sample_valid_la <= 1'b0;
downsampler_counter_la <= 32'h0;
end else begin
if (downsampler_counter_la < divider_counter_la ) begin
downsampler_counter_la <= downsampler_counter_la + 1;
sample_valid_la <= 1'b0;
end else begin
downsampler_counter_la <= 32'h0;
sample_valid_la <= 1'b1;
end
end
end
// upsampler pattern generator
always @(posedge clk) begin
if (reset == 1'b1) begin
upsampler_counter_pg <= 32'h0;
dac_read <= 1'b0;
end else begin
dac_read <= 1'b0;
if (upsampler_counter_pg < divider_counter_pg) begin
upsampler_counter_pg <= upsampler_counter_pg + 1;
end else begin
upsampler_counter_pg <= 32'h0;
dac_read <= 1'b1;
end
end
end
always @(posedge clk) begin
if (dac_valid == 1'b1) begin
data_r <= dac_data;
end
end
axi_logic_analyzer_trigger i_trigger (
.clk (clk),
.reset (reset),
.data (adc_data),
.trigger (trigger_m2),
.edge_detect_enable (edge_detect_enable),
.rise_edge_enable (rise_edge_enable),
.fall_edge_enable (fall_edge_enable),
.low_level_enable (low_level_enable),
.high_level_enable (high_level_enable),
.trigger_logic (trigger_logic),
.trigger_out (trigger_out));
axi_logic_analyzer_reg i_registers (
.clk (clk),
.reset (reset),
.divider_counter_la (divider_counter_la),
.divider_counter_pg (divider_counter_pg),
.io_selection (io_selection),
.edge_detect_enable (edge_detect_enable),
.rise_edge_enable (rise_edge_enable),
.fall_edge_enable (fall_edge_enable),
.low_level_enable (low_level_enable),
.high_level_enable (high_level_enable),
.trigger_delay (trigger_delay),
.trigger_logic (trigger_logic),
.clock_select (clock_select),
.overwrite_enable (overwrite_enable),
.overwrite_data (overwrite_data),
.input_data (adc_data),
.od_pp_n (od_pp_n),
// bus interface
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
// axi interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************

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library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc Normal file
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set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_state*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *downsampler_counter_* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *data_r_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *dac_read_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg* && IS_SEQUENTIAL}] \
-to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *trigger_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg* && IS_SEQUENTIAL}]

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library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_logic_analyzer
adi_ip_files axi_logic_analyzer [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_logic_analyzer_constr.xdc" \
"axi_logic_analyzer_reg.v" \
"axi_logic_analyzer_trigger.v" \
"axi_logic_analyzer.v" ]
adi_ip_properties axi_logic_analyzer
adi_ip_constraints axi_logic_analyzer [list \
"axi_logic_analyzer_constr.xdc" ]
ipx::remove_bus_interface {clk} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_logic_analyzer_reg (
input clk,
output reset,
output [31:0] divider_counter_la,
output [31:0] divider_counter_pg,
output [15:0] io_selection,
output [17:0] edge_detect_enable,
output [17:0] rise_edge_enable,
output [17:0] fall_edge_enable,
output [17:0] low_level_enable,
output [17:0] high_level_enable,
output [31:0] trigger_delay,
output trigger_logic,
output clock_select,
output [15:0] overwrite_enable,
output [15:0] overwrite_data,
input [15:0] input_data,
output [15:0] od_pp_n,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// internal registers
reg [31:0] up_version = 32'h00010000;
reg [31:0] up_scratch = 0;
reg [31:0] up_divider_counter_la = 0;
reg [31:0] up_divider_counter_pg = 0;
reg [15:0] up_io_selection = 16'h0;
reg [17:0] up_edge_detect_enable = 0;
reg [17:0] up_rise_edge_enable = 0;
reg [17:0] up_fall_edge_enable = 0;
reg [17:0] up_low_level_enable = 0;
reg [17:0] up_high_level_enable = 0;
reg [31:0] up_trigger_delay = 0;
reg up_trigger_logic = 0;
reg up_clock_select = 0;
reg [15:0] up_overwrite_enable = 0;
reg [15:0] up_overwrite_data = 0;
reg [15:0] up_od_pp_n = 0;
wire [15:0] up_input_data;
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_divider_counter_la <= 'd0;
up_divider_counter_pg <= 'd0;
up_edge_detect_enable <= 'd0;
up_rise_edge_enable <= 'd0;
up_fall_edge_enable <= 'd0;
up_low_level_enable <= 'd0;
up_high_level_enable <= 'd0;
up_trigger_delay <= 'd0;
up_trigger_logic <= 'd0;
up_clock_select <= 'd0;
up_overwrite_enable <= 'd0;
up_overwrite_data <= 'd0;
up_io_selection <= 16'h0;
up_od_pp_n <= 16'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
up_divider_counter_la <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
up_divider_counter_pg <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
up_io_selection <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
up_edge_detect_enable <= up_wdata[17:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
up_rise_edge_enable <= up_wdata[17:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
up_fall_edge_enable <= up_wdata[17:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
up_low_level_enable <= up_wdata[17:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
up_high_level_enable <= up_wdata[17:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
up_trigger_delay <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
up_trigger_logic <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
up_clock_select <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
up_overwrite_enable <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'he)) begin
up_overwrite_data <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_od_pp_n <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch;
5'h2: up_rdata <= up_divider_counter_la;
5'h3: up_rdata <= up_divider_counter_pg;
5'h4: up_rdata <= {16'h0,up_io_selection};
5'h5: up_rdata <= {14'h0,up_edge_detect_enable};
5'h6: up_rdata <= {14'h0,up_rise_edge_enable};
5'h7: up_rdata <= {14'h0,up_fall_edge_enable};
5'h8: up_rdata <= {14'h0,up_low_level_enable};
5'h9: up_rdata <= {14'h0,up_high_level_enable};
5'ha: up_rdata <= up_trigger_delay;
5'hb: up_rdata <= {31'h0,up_trigger_logic};
5'hc: up_rdata <= {31'h0,up_clock_select};
5'hd: up_rdata <= {16'h0,up_overwrite_enable};
5'he: up_rdata <= {16'h0,up_overwrite_data};
5'hf: up_rdata <= {16'h0,up_input_data};
5'h10: up_rdata <= {16'h0,up_od_pp_n};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
ad_rst i_core_rst_reg (.preset(!up_rstn), .clk(clk), .rst(reset));
up_xfer_cntrl #(.DATA_WIDTH(252)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_od_pp_n, // 16
up_overwrite_data, // 16
up_overwrite_enable, // 16
up_clock_select, // 1
up_trigger_logic, // 1
up_trigger_delay, // 32
up_high_level_enable, // 18
up_low_level_enable, // 18
up_fall_edge_enable, // 18
up_rise_edge_enable, // 18
up_edge_detect_enable, // 18
up_io_selection, // 16
up_divider_counter_pg, // 32
up_divider_counter_la}), // 32
.up_xfer_done (),
.d_rst (1'b0),
.d_clk (clk),
.d_data_cntrl ({ od_pp_n, // 16
overwrite_data, // 16
overwrite_enable, // 16
clock_select, // 1
trigger_logic, // 1
trigger_delay, // 32
high_level_enable, // 18
low_level_enable, // 18
fall_edge_enable, // 18
rise_edge_enable, // 18
edge_detect_enable, // 18
io_selection, // 16
divider_counter_pg, // 32
divider_counter_la})); // 32
up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
// up interface
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_status(up_input_data),
// device interface
.d_rst(1'd0),
.d_clk(clk),
.d_data_status(input_data));
endmodule
// ***************************************************************************
// ***************************************************************************

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_logic_analyzer_trigger (
input clk,
input reset,
input [15:0] data,
input [ 1:0] trigger,
input [17:0] edge_detect_enable,
input [17:0] rise_edge_enable,
input [17:0] fall_edge_enable,
input [17:0] low_level_enable,
input [17:0] high_level_enable,
input trigger_logic,
output trigger_out);
reg [ 17:0] data_m1 = 'd0;
reg [ 17:0] low_level = 'd0;
reg [ 17:0] high_level = 'd0;
reg [ 17:0] edge_detect = 'd0;
reg [ 17:0] rise_edge = 'd0;
reg [ 17:0] fall_edge = 'd0;
reg [ 31:0] delay_count = 'd0;
reg trigger_active;
assign trigger_out = trigger_active;
// trigger logic:
// 0 OR
// 1 AND
always @(*) begin
case (trigger_logic)
0: trigger_active = | ((edge_detect & edge_detect_enable) |
(rise_edge & rise_edge_enable) |
(fall_edge & fall_edge_enable) |
(low_level & low_level_enable) |
(high_level & high_level_enable));
1: trigger_active = | (((edge_detect & edge_detect_enable) | !(|edge_detect_enable)) &
((rise_edge & rise_edge_enable) | !(|rise_edge_enable)) &
((fall_edge & fall_edge_enable) | !(|fall_edge_enable)) &
((low_level & low_level_enable) | !(|low_level_enable)) &
((high_level & high_level_enable) | !(|high_level_enable)));
default: trigger_active = 1'b1;
endcase
end
// internal signals
always @(posedge clk) begin
if (reset == 1'b1) begin
data_m1 <= 'd0;
edge_detect <= 'd0;
rise_edge <= 'd0;
fall_edge <= 'd0;
low_level <= 'd0;
high_level <= 'd0;
end else begin
data_m1 <= {trigger, data} ;
edge_detect <= data_m1 ^ {trigger, data};
rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data};
fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data};
low_level <= ~{trigger, data};
high_level <= {trigger, data};
end
end
endmodule
// ***************************************************************************
// ***************************************************************************