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common/ad_serdes_in.v: Add US/US+ support

main
Laszlo Nagy 2019-06-06 06:58:05 +01:00 committed by Laszlo Nagy
parent 4972e5c42d
commit 65d39b9164
1 changed files with 111 additions and 3 deletions
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114
library/xilinx/common/ad_serdes_in.v
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@ -56,14 +56,14 @@ module ad_serdes_in #(
// data interface
output [(DATA_WIDTH-1):0] data_s0,
output [(DATA_WIDTH-1):0] data_s0, // last bit received
output [(DATA_WIDTH-1):0] data_s1,
output [(DATA_WIDTH-1):0] data_s2,
output [(DATA_WIDTH-1):0] data_s3,
output [(DATA_WIDTH-1):0] data_s4,
output [(DATA_WIDTH-1):0] data_s5,
output [(DATA_WIDTH-1):0] data_s6,
output [(DATA_WIDTH-1):0] data_s7,
output [(DATA_WIDTH-1):0] data_s7, // 1st bit received
input [(DATA_WIDTH-1):0] data_in_p,
input [(DATA_WIDTH-1):0] data_in_n,
@ -85,6 +85,16 @@ module ad_serdes_in #(
localparam ULTRASCALE_PLUS = 3;
localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR";
localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" :
"UNSUPPORTED";
localparam SIM_DEVICE_IDELAYCTRL = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" :
FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE" :
"UNSUPPORTED";
// internal signals
wire [(DATA_WIDTH-1):0] data_in_ibuf_s;
@ -97,7 +107,9 @@ module ad_serdes_in #(
generate
if (IODELAY_CTRL == 1) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
IDELAYCTRL #(
.SIM_DEVICE(SIM_DEVICE_IDELAYCTRL)
) i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
@ -193,6 +205,102 @@ module ad_serdes_in #(
end
endgenerate
generate if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
IBUFDS i_ibuf (
.I (data_in_p[l_inst]),
.IB (data_in_n[l_inst]),
.O (data_in_ibuf_s[l_inst]));
wire div_dld;
reg [4:0] vtc_cnt = {5{1'b1}};
sync_event sync_load(
.in_clk (up_clk),
.in_event (up_dld[l_inst]),
.out_clk (div_clk),
.out_event (div_dld)
);
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #(
.CASCADE ("NONE"), // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
.DELAY_FORMAT ("TIME"), // Units of the DELAY_VALUE (COUNT, TIME)
.DELAY_SRC ("IDATAIN"), // Delay input (DATAIN, IDATAIN)
.DELAY_TYPE ("VAR_LOAD"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
.DELAY_VALUE (0), // Input delay value setting
.IS_CLK_INVERTED (1'b0), // Optional inversion for CLK
.IS_RST_INVERTED (1'b0), // Optional inversion for RST
.REFCLK_FREQUENCY (500.0), // IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
.SIM_DEVICE (SIM_DEVICE), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
// ULTRASCALE_PLUS_ES2)
.UPDATE_MODE ("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
)
i_idelay(
.CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade
.CNTVALUEOUT(up_drdata[((5*l_inst)+4):(5*l_inst)]), // 9-bit output: Counter value output
.DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output
.CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
.CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
.CE (1'b0), // 1-bit input: Active high enable increment/decrement input
.CLK (div_clk), // 1-bit input: Clock input
.CNTVALUEIN(up_dwdata[((5*l_inst)+4):(5*l_inst)]), // 9-bit input: Counter value input
.DATAIN (1'b0), // 1-bit input: Data input from the logic
.EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT
.IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF
.INC (1'b0), // 1-bit input: Increment / Decrement tap delay input
.LOAD (ld_cnt), // 1-bit input: Load DELAY_VALUE input
.RST (rst) // 1-bit input: Asynchronous Reset to the DELAY_VALUE
);
always @(posedge div_clk) begin
if (div_dld) begin
vtc_cnt <= 'h0;
end else if (~(&vtc_cnt)) begin
vtc_cnt <= vtc_cnt + 1;
end
end
assign en_vtc = &vtc_cnt;
assign ld_cnt = ~vtc_cnt[4] & (&vtc_cnt[3:0]);
ISERDESE3 #(
.DATA_WIDTH (8), // Parallel data width (4,8)
.FIFO_ENABLE ("FALSE"), // Enables the use of the FIFO
.FIFO_SYNC_MODE ("FALSE"), // Enables the use of internal 2-stage synchronizers on the FIFO
.IS_CLK_B_INVERTED (1'b0), // Optional inversion for CLK_B
.IS_CLK_INVERTED (1'b0), // Optional inversion for CLK
.IS_RST_INVERTED (1'b0), // Optional inversion for RST
.SIM_DEVICE (SIM_DEVICE) // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
// ULTRASCALE_PLUS_ES2)
)
i_iserdes(
.FIFO_EMPTY (), // 1-bit output: FIFO empty flag
.INTERNAL_DIVCLK (), // 1-bit output: Internally divided down clock used when FIFO is
// disabled (do not connect)
.Q ({data_s0[l_inst],
data_s1[l_inst],
data_s2[l_inst],
data_s3[l_inst],
data_s4[l_inst],
data_s5[l_inst],
data_s6[l_inst],
data_s7[l_inst]}), // 8-bit registered output
.CLK (clk), // 1-bit input: High-speed clock
.CLKDIV (div_clk), // 1-bit input: Divided Clock
.CLK_B (~clk), // 1-bit input: Inversion of High-speed clock CLK
.D (data_in_idelay_s[l_inst]), // 1-bit input: Serial Data Input
.FIFO_RD_CLK (div_clk), // 1-bit input: FIFO read clock
.FIFO_RD_EN (1'b1), // 1-bit input: Enables reading the FIFO when asserted
.RST (rst) // 1-bit input: Asynchronous Reset
);
end
end
endgenerate
endmodule