zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_dmac: Add axis_last control signal to the Master AXI Streaming interface 

This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
main
Istvan Csomortani 2015-05-06 13:12:28 +03:00
parent 4f75414a1a
commit 65af205d6b
3 changed files with 24 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
library/axi_dmac/axi_dmac.v
View File

@ -153,6 +153,7 @@ module axi_dmac (
input m_axis_ready,
output m_axis_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
@ -255,9 +256,13 @@ wire [1:0] up_irq_source_clear;
reg up_dma_req_valid = 1'b0;
wire up_dma_req_ready;
reg [1:0] up_transfer_id;
reg [1:0] up_transfer_id_eot;
reg [3:0] up_transfer_done_bitmap;
reg [1:0] up_transfer_id = 2'b0;
reg [1:0] up_transfer_id_eot = 2'b0;
reg [3:0] up_transfer_done_bitmap = 4'b0;
reg [3:0] up_axis_xlast_bitmap = 4'b0;
reg up_axis_xlast = 1'b0;
reg up_axis_xlast_en = 1'b0;
wire m_axis_last_s;
reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
@ -383,7 +388,11 @@ begin
12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
12'h103: if (C_CYCLIC) up_dma_cyclic <= up_wdata[0];
12'h103: begin
if (C_CYCLIC) up_dma_cyclic <= up_wdata[0];
up_axis_xlast_en <= up_wdata[1];
up_axis_xlast <= up_wdata[2];
end
12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
@ -412,7 +421,7 @@ begin
12'h100: up_rdata <= {up_pause, up_enable};
12'h101: up_rdata <= up_transfer_id;
12'h102: up_rdata <= up_dma_req_valid;
12'h103: up_rdata <= {31'h00, up_dma_cyclic}; // Flags
12'h103: up_rdata <= {31'h00, up_axis_xlast, up_axis_xlast_en, up_dma_cyclic}; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
@ -443,14 +452,18 @@ begin
if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
up_transfer_id <= up_transfer_id + 1'b1;
up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
up_axis_xlast_bitmap[up_transfer_id] <= up_axis_xlast;
end
if (up_eot == 1'b1) begin
up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
up_axis_xlast_bitmap[up_transfer_id_eot] <= 1'b0;
end
end
end
assign m_axis_last = (up_axis_xlast_en == 1'b1) ? (up_axis_xlast_bitmap[dest_data_id] & m_axis_last_s) : m_axis_last_s;
wire dma_req_valid;
wire dma_req_ready;
wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
@ -595,6 +608,7 @@ dmac_request_arb #(
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.m_axis_last(m_axis_last_s),
.m_axis_xfer_req(m_axis_xfer_req),

2
library/axi_dmac/dest_axi_stream.v
View File

@ -55,6 +55,7 @@ module dmac_dest_axi_stream (
input m_axis_ready,
output m_axis_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output m_axis_last,
output fifo_ready,
input fifo_valid,
@ -108,6 +109,7 @@ dmac_data_mover # (
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.m_axi_last(m_axis_last),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)

4
library/axi_dmac/request_arb.v
View File

@ -109,6 +109,7 @@ module dmac_request_arb (
input m_axis_ready,
output m_axis_valid,
output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
@ -522,7 +523,8 @@ dmac_dest_axi_stream #(
.m_axis_valid(m_axis_valid),
.m_axis_ready(m_axis_ready),
.m_axis_data(m_axis_data)
.m_axis_data(m_axis_data),
.m_axis_last(m_axis_last)
);
end else begin