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cftl_cip: Initial check in. 

Project cftl_cip supports the following Circuits from the Lab pmods:
 + EVAL-CN0350-PMDZ
 + EVAL-CN0335-PMDZ
 + EVAL-CN0336-PMDZ
 + EVAL-CN0337-PMDZ
Note: Additional testing needed!
main
Istvan Csomortani 2015-01-23 18:29:32 +02:00
parent 463a3bbc88
commit 659e0cca4e
7 changed files with 692 additions and 0 deletions
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317
library/util_pmod_adc/util_pmod_adc.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This core supports pmods with AD7091R, it controls a simple three wire
// SPI interface with an additional control line for conversion start
// NOTE: The maximum clock rate is 100 Mhz, the SPI interface clock is always
// half of the core's clock.
`timescale 1ns/1ns
module util_pmod_adc (
// clock and reset signals
clk,
reset,
// dma interface
adc_data,
adc_valid,
adc_enable,
adc_dbg,
// adc interface (clk, data, cs and conversion start)
adc_sdo,
adc_sclk,
adc_cs_n,
adc_convst_n
);
// parameters and local parameters
parameter real FPGA_CLOCK_FREQ = 100; // FPGA clock frequency [MHz] NOTE: this is the maximum supported frequency
parameter real ADC_CYCLE_TIME = 1.000; // minimum time between two ADC conversions [us]
parameter real ADC_CONVST_TIME = 0.010; // minimum time to keep /CONVST low [us]
parameter real ADC_CONVERT_TIME = 0.650; // conversion time [us]
parameter ADC_SCLK_PERIODS = 5'd12;
parameter ADC_RESET_SCLK_PERIODS = 4'd3;
// ADC states
localparam ADC_SW_RESET_STATE = 8'b00000001;
localparam ADC_IDLE_STATE = 8'b00000010;
localparam ADC_START_CNV_STATE = 8'b00000100;
localparam ADC_WAIT_CNV_DONE_STATE = 8'b00001000;
localparam ADC_WAIT_DATA_VALID_STATE = 8'b00010000;
localparam ADC_READ_CNV_RESULT = 8'b00100000;
localparam ADC_END_CNV_STATE = 8'b01000000;
localparam ADC_DATAREADY_STATE = 8'b10000000;
// ADC timing
localparam [6:0] ADC_CYCLE_CNT = FPGA_CLOCK_FREQ * ADC_CYCLE_TIME - 1;
localparam [6:0] ADC_CONVST_CNT = FPGA_CLOCK_FREQ * ADC_CONVST_TIME - 1;
localparam [6:0] ADC_CONVERT_CNT = FPGA_CLOCK_FREQ * ADC_CONVERT_TIME - 1;
// clock and reset signals
input clk; // system clock (100 MHz)
input reset; // active high reset signal
// dma interface
output [15:0] adc_data;
output adc_valid;
output adc_enable;
output [ 7:0] adc_dbg; // signals that the first data acquisition has been performed
// adc interface
input adc_sdo;
output adc_sclk;
output adc_cs_n;
output adc_convst_n;
reg [15:0] adc_data = 'd0;
reg adc_valid = 'b0;
reg adc_enable = 'b0;
reg [ 7:0] adc_dbg = 'b0;
reg adc_clk = 'd0;
reg [ 7:0] adc_state = 'b0; // current state for the ADC control state machine
reg [ 7:0] adc_next_state = 'b0; // next state for the ADC control state machine
reg [ 7:0] adc_state_nc_m1 = 'b0; // current state for the ADC state machine in the ADC clock domain sampled on the falling edge
reg [ 7:0] adc_state_pc_m1 = 'b0; // current state for the ADC state machine in the ADC clock domain sampled on the rising edge
reg [ 6:0] adc_tcycle_cnt = 'b0;
reg [ 6:0] adc_tconvst_cnt = 'b0;
reg [ 6:0] adc_tconvert_cnt = 'b0;
reg [ 4:0] sclk_clk_cnt = 'b0;
reg adc_cnv_s = 'b0;
reg adc_clk_en = 1'b0;
reg adc_cs_n_s = 'b0;
reg [15:0] adc_data_s = 'b0;
reg adc_sw_reset = 'b0;
reg data_rd_ready_s = 'b0;
// Assign/Always Blocks
assign adc_sclk = adc_clk & adc_clk_en;
assign adc_cs_n = adc_cs_n_s;
assign adc_convst_n = adc_cnv_s;
always @(negedge clk) begin
if(reset == 1'b1) begin
adc_valid <= 1'b0;
adc_enable <= 1'b0;
end else begin
adc_valid <= data_rd_ready_s;
adc_enable <= 1'b1;
if(adc_valid == 1'b1) begin
adc_data <= adc_data_s;
end
end
end
// generate ADC clock, max rate is 50 Mhz
always @(posedge clk) begin
adc_clk<= ~adc_clk;
end
// update the ADC timing counters
always @(posedge clk)
begin
if(reset == 1'b1) begin
adc_tcycle_cnt <= 0;
adc_tconvst_cnt <= ADC_CONVST_CNT;
adc_tconvert_cnt <= ADC_CONVERT_CNT;
end else begin
if(adc_tcycle_cnt != 1'b0) begin
adc_tcycle_cnt <= adc_tcycle_cnt - 7'h1;
end
else if(adc_state == ADC_IDLE_STATE || adc_state == ADC_SW_RESET_STATE) begin
adc_tcycle_cnt <= ADC_CYCLE_CNT;
end
if(adc_state == ADC_START_CNV_STATE) begin
adc_tconvst_cnt <= adc_tconvst_cnt - 7'h1;
end
else begin
adc_tconvst_cnt <= ADC_CONVST_CNT;
end
if(adc_state == ADC_WAIT_CNV_DONE_STATE) begin
adc_tconvert_cnt <= adc_tconvert_cnt - 7'h1;
end
else begin
adc_tconvert_cnt <= ADC_CONVERT_CNT;
end
end
end
// determine when the ADC clock is valid to be sent to the ADC
always @(negedge adc_clk) begin
adc_state_nc_m1 <= adc_state;
adc_clk_en <= ((adc_state_nc_m1 == ADC_WAIT_DATA_VALID_STATE) ||
(adc_state_nc_m1 == ADC_READ_CNV_RESULT) &&
((sclk_clk_cnt != 0) ||
((adc_sw_reset == 1'b1) &&
(sclk_clk_cnt == ADC_SCLK_PERIODS - ADC_RESET_SCLK_PERIODS)))) ? 1'b1 : 1'b0;
end
// read data from the ADC
always @(negedge adc_clk) begin
adc_state_pc_m1 <= adc_state;
if(adc_clk_en == 1'b1) begin
adc_data_s <= {3'b0, adc_data_s[11:0], adc_sdo};
sclk_clk_cnt <= sclk_clk_cnt - 5'h1;
end
else if(adc_state_pc_m1 != ADC_READ_CNV_RESULT && adc_state_pc_m1 != ADC_END_CNV_STATE) begin
adc_data_s <= 16'h0;
sclk_clk_cnt <= ADC_SCLK_PERIODS - 1;
end
end
// update the ADC current state and the control signals
always @(posedge clk) begin
if(reset == 1'b1) begin
adc_state <= ADC_SW_RESET_STATE;
adc_dbg <= 1'b0;
end
else begin
adc_state <= adc_next_state;
adc_dbg <= adc_state;
case (adc_state)
ADC_SW_RESET_STATE: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b1;
data_rd_ready_s <= 1'b0;
adc_sw_reset <= 1'b1;
end
ADC_IDLE_STATE: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b1;
data_rd_ready_s <= 1'b0;
adc_sw_reset <= 1'b0;
end
ADC_START_CNV_STATE: begin
adc_cnv_s <= 1'b0;
adc_cs_n_s <= 1'b1;
data_rd_ready_s <= 1'b0;
end
ADC_WAIT_CNV_DONE_STATE: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b1;
data_rd_ready_s <= 1'b0;
end
ADC_WAIT_DATA_VALID_STATE: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b1;
data_rd_ready_s <= 1'b0;
end
ADC_READ_CNV_RESULT: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b0;
data_rd_ready_s <= 1'b0;
end
ADC_END_CNV_STATE: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b0;
data_rd_ready_s <= 1'b0;
end
ADC_DATAREADY_STATE: begin
adc_cnv_s <= 1'b1;
adc_cs_n_s <= 1'b0;
data_rd_ready_s <= 1'b1;
end
endcase
end
end
// update the ADC next state
always @(adc_state, adc_tcycle_cnt, adc_tconvst_cnt, adc_tconvert_cnt, sclk_clk_cnt, adc_sw_reset) begin
adc_next_state <= adc_state;
case (adc_state)
ADC_SW_RESET_STATE: begin
adc_next_state <= ADC_START_CNV_STATE;
end
ADC_IDLE_STATE: begin
if(adc_tcycle_cnt == 0) begin
adc_next_state <= ADC_START_CNV_STATE;
end
end
ADC_START_CNV_STATE: begin
if(adc_tconvst_cnt == 0) begin
adc_next_state <= ADC_WAIT_CNV_DONE_STATE;
end
end
ADC_WAIT_CNV_DONE_STATE: begin
if(adc_tconvert_cnt == 0) begin
adc_next_state <= ADC_WAIT_DATA_VALID_STATE;
end
end
ADC_WAIT_DATA_VALID_STATE: begin
adc_next_state <= ADC_READ_CNV_RESULT;
end
ADC_READ_CNV_RESULT: begin
if((sclk_clk_cnt == 0) || ((adc_sw_reset == 1'b1) && (sclk_clk_cnt == ADC_SCLK_PERIODS - ADC_RESET_SCLK_PERIODS))) begin
adc_next_state <= ADC_END_CNV_STATE;
end
end
ADC_END_CNV_STATE: begin
adc_next_state <= ADC_DATAREADY_STATE;
end
ADC_DATAREADY_STATE: begin
adc_next_state <= ADC_IDLE_STATE;
end
default: begin
adc_next_state <= ADC_IDLE_STATE;
end
endcase
end
endmodule

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library/util_pmod_adc/util_pmod_adc_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_pmod_adc
adi_ip_files util_pmod_adc [list \
"util_pmod_adc.v"
]
adi_ip_properties_lite util_pmod_adc
# set reset polarity to high
set reset_inf [ipx::get_bus_interfaces "signal_reset" -of_objects [ipx::current_core]]
set reset_polarity [ipx::get_bus_parameters "POLARITY" -of_objects $reset_inf]
set_property value "ACTIVE_HIGH" $reset_polarity
ipx::save_core [ipx::current_core]

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# pmod interface
set pmod_cs [create_bd_port -dir O pmod_cs]
set pmod_miso [create_bd_port -dir I pmod_miso]
set pmod_clk [create_bd_port -dir O pmod_clk]
set pmod_convst [create_bd_port -dir O pmod_convst]
# interrupts
set ad_ad7091r_dma_intr [create_bd_port -dir O ad_ad7091r_dma_intr]
# instances
set ad_ad7091r_core [create_bd_cell -type ip -vlnv analog.com:user:util_pmod_adc:1.0 ad_ad7091r_core]
set ad_ad7091r_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 ad_ad7091r_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $ad_ad7091r_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $ad_ad7091r_dma
set ad_ad7091r_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ad_ad7091r_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $ad_ad7091r_dma_interconnect
# additional configurations
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_interconnect
# up axi interface connection
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07 [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins ad_ad7091r_dma/s_axi]
connect_bd_intf_net -intf_net ad_ad7091r_dma_interconnect_m00_axi [get_bd_intf_pins ad_ad7091r_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
connect_bd_intf_net -intf_net ad_ad7091r_dma_interconnect_s00_axi [get_bd_intf_pins ad_ad7091r_dma_interconnect/S00_AXI] [get_bd_intf_pins ad_ad7091r_dma/m_dest_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_dma_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_dma_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_dma_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_dma/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_dma/fifo_wr_clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_dma/m_dest_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins ad_ad7091r_core/clk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins ad_ad7091r_dma_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins ad_ad7091r_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins ad_ad7091r_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins ad_ad7091r_dma/s_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins ad_ad7091r_dma/m_dest_axi_aresetn] $sys_100m_resetn_source
connect_bd_net -net sys_100m_reset [get_bd_pins ad_ad7091r_core/reset] [get_bd_pins sys_rstgen/peripheral_reset]
connect_bd_net -net ad_ad7091r_data [get_bd_pins ad_ad7091r_core/adc_data] [get_bd_pins ad_ad7091r_dma/fifo_wr_din]
connect_bd_net -net ad_ad7091r_dvalid [get_bd_pins ad_ad7091r_core/adc_valid] [get_bd_pins ad_ad7091r_dma/fifo_wr_en]
connect_bd_net -net ad_ad7091r_sdo [get_bd_pins ad_ad7091r_core/adc_sdo] [get_bd_ports pmod_miso]
connect_bd_net -net ad_ad7091r_sclk [get_bd_pins ad_ad7091r_core/adc_sclk] [get_bd_ports pmod_clk]
connect_bd_net -net ad_ad7091r_csn [get_bd_pins ad_ad7091r_core/adc_cs_n] [get_bd_ports pmod_cs]
connect_bd_net -net ad_ad7091r_convstn [get_bd_pins ad_ad7091r_core/adc_convst_n] [get_bd_ports pmod_convst]
connect_bd_net -net ad_ad7091r_dma_irq [get_bd_pins ad_ad7091r_dma/irq] [get_bd_ports ad_ad7091r_dma_intr]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x43010000 $sys_addr_cntrl_space [get_bd_addr_segs ad_ad7091r_dma/s_axi/axi_lite] SEG_data_ad_ad7091r_dma
create_bd_addr -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces ad_ad7091r_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm

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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/cftl_cip_bd.tcl

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# pmod connector
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports pmod_ad7091r_cs]
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports pmod_ad7091r_miso]
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports pmod_ad7091r_clk]
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports pmod_ad7091r_convst]

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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create cftl_custom_zed
adi_project_files cftl_custom_zed [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
"$ad_hdl_dir/library/common/ad_iobuf.v"]
adi_project_run cftl_custom_zed

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// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc,
pmod_ad7091r_cs,
pmod_ad7091r_miso,
pmod_ad7091r_clk,
pmod_ad7091r_convst);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [ 3:0] DDR_dm;
inout [31:0] DDR_dq;
inout [ 3:0] DDR_dqs_n;
inout [ 3:0] DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0] FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
output pmod_ad7091r_cs;
input pmod_ad7091r_miso;
output pmod_ad7091r_clk;
output pmod_ad7091r_convst;
// internal signals
wire [31:0] gpio_i;
wire [31:0] gpio_o;
wire [31:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [15:0] ps_intrs;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dt(gpio_t),
.di(gpio_o),
.do(gpio_i),
.dio(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.di(iic_mux_scl_o_s),
.do(iic_mux_scl_i_s),
.dio(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.di(iic_mux_sda_o_s),
.do(iic_mux_sda_i_s),
.dio(iic_mux_sda));
system_wrapper i_system_wrapper (
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_I (iic_mux_scl_i_s),
.iic_mux_scl_O (iic_mux_scl_o_s),
.iic_mux_scl_T (iic_mux_scl_t_s),
.iic_mux_sda_I (iic_mux_sda_i_s),
.iic_mux_sda_O (iic_mux_sda_o_s),
.iic_mux_sda_T (iic_mux_sda_t_s),
.ps_intr_0 (ps_intrs[0]),
.ps_intr_1 (ps_intrs[1]),
.ps_intr_2 (ps_intrs[2]),
.ps_intr_3 (ps_intrs[3]),
.ps_intr_4 (ps_intrs[4]),
.ps_intr_5 (ps_intrs[5]),
.ps_intr_6 (ps_intrs[6]),
.ps_intr_7 (ps_intrs[7]),
.ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]),
.ps_intr_10 (ps_intrs[10]),
.ps_intr_11 (ps_intrs[11]),
.ps_intr_12 (ps_intrs[12]),
.ps_intr_13 (ps_intrs[13]),
.iic_fmc_intr (ps_intrs[11]),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.pmod_cs (pmod_ad7091r_cs),
.pmod_miso (pmod_ad7091r_miso),
.pmod_clk (pmod_ad7091r_clk),
.pmod_convst (pmod_ad7091r_convst),
.ad_ad7091r_dma_intr (ps_intrs[13]));
endmodule
// ***************************************************************************
// ***************************************************************************