data_offload: Update README and generic block design
Istvan Csomortani
Mihaita Nagy
parent
26518cdace
commit
6516b09a31
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@ -8,10 +8,13 @@ Data offload module for high-speed converters:
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**NOTE**: This IP will always have a storage unit (internal or external to the FPGA) and is
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designed to handle high data rates. If your data paths will run in a lower data
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rate, and your intention is just to transfer the data to another clock domain or
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to adjust the bus width of the data path, you must to use another IP.
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to adjust the bus width of the data path, you may want to check out the util_axis_fifo or
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util_axis_fifo_asym IPs.
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The initialization and data transfer looks as follows:
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* in case of DAC, the DMA initialize the storage unit, after that the controller
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will push the data to the DAC interface in one-shot or cyclic way, until the next initialization
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will push the data to the DAC interface in one-shot or cyclic way
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* in case of ADC, the DMA request a transfer, the controller will save the data into
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the storage unit, after that will push it to the DMA
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@ -48,7 +51,7 @@ URAM, external memory etc.)
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## Block diagram
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## Parameters
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@ -57,28 +60,19 @@ URAM, external memory etc.)
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|ID | integer | 0 | Instance ID number |
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|MEM_TYPE | [ 0:0] | 0 | Define the used storage type: FPGA RAM - 0; external DDR - 1 |
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|MEM_SIZE | [31:0] | 1024 | Define the size of the storage element |
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|RX_ENABLE | [ 0:0] | 1 | Enable/disable the ADC path |
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|RX_FRONTEND_IF | [ 0:0] | 0 | M_AXIS - 0; FIFO_RD - 1 (FRONTEND is the DMA side) |
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|RX_BACKEND_IF | [ 0:0] | 0 | S_AXIS - 0; FIFO_WR - 1 (BACKEND is the device side) |
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|RX_FRONTEND_DATA_WIDTH| integer | 64 | The data width of the RX frontend interface, it depends of the dma configuration |
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|RX_BACKEND_DATA_WIDTH | integer | 64 | The data width of the RX backend interface, it depends of the device core configuration |
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|RX_RAW_DATA_EN | [ 0:0] | 1 | Enables a gearbox module in the RX path, so only the raw samples will be stored in the memory. |
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|TX_ENABLE | [ 0:0] | 1 | Enable/disable the DAC path |
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|TX_FRONTEND_IF | [ 0:0] | 0 | S_AXIS - 0; FIFO_WR - 1 (FRONTEND is the DMA side) |
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|TX_BACKEND_IF | [ 0:0] | 0 | M_AXIS - 0; FIFO_RD - 1 (BACKEND is the device side) |
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|TX_FRONTEND_DATA_WIDTH| integer | 64 | The data width of the TX frontend interface, it depends of the dma configuration |
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|TX_BACKEND_DATA_WIDTH | integer | 64 | The data width of the TX backend interface, it depends of the device core configuration |
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|TX_RAW_DATA_EN | [ 0:0] | 1 | Enables a gearbox module in the TX path, so only the raw samples will be stored in the memory. |
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|MEMC_UIF_TYPE | [ 0:0] | 0 | AXI_MM - 0; AVL_MM - 1 |
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|MEMC_UIF_DATA_WIDTH | [ 0:0] | 512 | The valid data depends on the DDRx memory controller IP. |
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|MEMC_UIF_ADDRESS_WIDTH| integer | 25 | The valid data depends on the DDRx memory controller IP. |
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|MEMC_RX_BADDRESS | [31:0] |32'h000000 | DDR base address for the ADC data. |
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|MEMC_TX_BADDRESS | [31:0] |32'h100000 | DDR base address for the DAC data. |
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|TX_OR_RXN_PATH | [ 0:0] | 1 | If set TX path enabled, otherwise RX |
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|SRC_DATA_WIDTH | integer | 64 | The data width of the source interface |
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|SRC_RAW_DATA_EN | [ 0:0] | 0 | Enable if the data path does extend samples to 16 bits |
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|SRC_ADDR_WIDTH | integer | 8 | The address width of the source interface, should be defined relative to the MEM_SIZE (MEM_SIZE/SRC_DATA_WIDTH/8) |
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|DST_ADDR_WIDTH | integer | 7 | The address width of the source interface, should be defined relative to the MEM_SIZE (MEM_SIZE/DST_DATA_WIDTH/8) |
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|DST_DATA_WIDTH | integer | 64 | The data width of the destination interface |
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|DST_RAW_DATA_EN | [ 0:0] | 0 | Enable if the data path does extend samples to 16 bits |
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|DST_CYCLIC_EN | [ 0:0] | 0 | Enables CYCLIC mode for destinations like DAC |
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|AUTO_BRINUP | [ 0:0] | 0 | If enabled the IP runs automatically after bootup |
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## Interfaces
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### AXI4 Lite Memory Mapped Slave (S_AXI4_LITE)
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This interface is used to access the register map.
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@ -145,10 +139,11 @@ input s_axi_rready
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### Supported data interfaces
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**NOTE**: All the data interfaces for the streams should be supported by both
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frontend (DMA) and backend (device) side. Although in general the FIFO_RD and
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FIFO_WR interfaces can be found in the device side, and the AXIS interfaces on
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the DMA side.
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**NOTE**: To simplify the design both the source and destination data interface is
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an AXI4 streaming interface. A FIFO write (ADC) interface can be treated as AXI4
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stream where only the master controles the data rate (s_axis_ready is always asserted),
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and a FIFO read (DAC) interface can be treated as an AXI4 stream where only the slave
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controles the data rate. (m_axis_valid is always asserted).
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#### AXI4 Stream interface (S_AXIS | M_AXIS)
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@ -158,11 +153,6 @@ the transmit DMA or ADC device.
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* The AXI Stream Master (M_AXIS) interface is used to transmit AXI stream
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to receive DMA or DAC device
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**NOTE**: In all cases the data stream is controlled by the device. Although the
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generic AXI Stream interface standard supports back-pressure, in our cases none
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the DAC, nore the ADC can wait for data. The DMA always have to be ready, samples
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will be lost otherwise!
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```verilog
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// NOTE: this reference is a master interface
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@ -188,58 +178,39 @@ and **axis_tkeep** will be used to indicate a partial last beat. This informatio
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should be transferred from the source domain to the sink domain, so we can read
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back the data from memory correctly.
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#### ADI FIFO interface
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#### FIFO source and destination interface to the storage unit
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This is non-blocking (no back-pressure) interface for the device cores.
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This is non-blocking (no back-pressure) interface for the storage unit,
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having an address bus too, so an ad_mem module can be connected directly to controller IP.
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To understand the motivation behind the name, let's look at a simple FIFO and its
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interfaces:
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A FIFO in general has a **write** and a **read** interface. In each case the
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interface is controlled by an external logic. Meaning that the FIFO will always
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act as slave. The only difference between the two interfaces is that in case of
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the **write** interface the data is driven by the master (we are writing into
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the FIFO), and in case of the **read** interface the data is driven by the slave
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(we are reading from the FIFO).
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To adapt this concept in our case, the device, which can be an ADC or a DAC,
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will always be the master. This means, that an ADC core will have a **fifo write**
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interface, and a DAC core will have a **fifo read** interface.
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In the same time, this means, that a processing core, which wants to interface
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a device core, need to have a **salve fifo write** or a **slave fifo read**
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interface, in other words needs to act as a FIFO.
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**Note:** The processing core (or DMA) can have an AXI stream interface too. To
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connect an AXIS stream interface to a FIFO interface the following mapping should
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be respected:
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* **fifo write to AXIS slave**:
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```verilog
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// the processing unit should always be READY, otherwise will lose data
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assign s_axis_valid = fifo_wr_valid;
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assign s_axis_data = fifo_wr_data;
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// This is a FIFO source interface - it's clocked on the source clock (s_axis_aclk)
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// Reset signal
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output fifo_src_resetn
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// write enable signal
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output fifo_src_wen
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// address bus for internal memory
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output [SRC_ADDR_WIDTH-1:0] fifo_src_waddr
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// source data bus
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output [SRC_DATA_WIDTH-1:0] fifo_src_wdata
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// write last, indicates the last valid transfer
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output fifo_src_wlast
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```
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* **fifo read to AXIS master**:
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```verilog
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// the processing unit should drive the data bus with the next valid data,
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// as the READY gets asserted
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assign m_axis_ready = fifo_rd_valid;
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assign fifo_rd_data = m_axis_data;
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// This is a FIFO destination interface - it's clocked on the destination clock (m_axis_aclk)
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// Reset signal
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output fifo_dst_resetn
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// read enable signal
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output fifo_dst_ren
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// indicate if the storage is ready to accept read requests
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output fifo_dst_ready,
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// address bus for internal memory
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output [DST_ADDR_WIDTH-1:0] fifo_dst_raddr
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// destination data bus
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output [DST_DATA_WIDTH-1:0] fifo_dst_rdata
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```
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User should be aware that in this case the AXI stream interface will loose the
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back pressure capability. The processing unit should be designed to compensate this
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scarcity.
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**NOTE**: the data stream should arrive in packed format to the core. The core
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does not care about number of channels or samples per beat. Result of this
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constraint is that the FIFO interface of the **Data Offload** module does not
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have any **enable** signals.
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```verilog
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// This is a Slave FIFO Read interface
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// device digital interface clock, or core clock
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@ -254,163 +225,6 @@ output [DATA_WIDTH-1:0] fifo_rd_data
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output fifo_rd_unf
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```
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```verilog
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// This is a Slave FIFO Write interface
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// device digital interface clock, or core clock
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input fifo_wr_clk
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// enables the channel -- in our case this is redundant -- maybe we do neet to use it at all
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input fifo_wr_enable
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// validates the data on the bus, it's driven by the device, indicates when the core drives the bus with new data
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input fifo_wr_valid
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// primary payload, its data width is equal with the channel's data width
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input [DATA_WIDTH-1:0] fifo_wr_data
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// indicates an overflow, the sink (offload FIFO in this case) can not consume the data fast enough
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output fifo_wr_ovf
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```
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#### AXI4 Memory Mapped master (M_AXI_MM)
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An AXI4 Memory Mapped interface, which transfer data into/from the external DDRx
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memory. This interface will be used explicitly with Xilinx FPGAs, to interface
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the MC (Memory Controller).
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```verilog
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/* clocks and resets */
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// clock signal of the interface, this is an independent clock from the sys_cpu, in general 200 MHz
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input axi_clk
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// synchronous active low reset
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input axi_resetn
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/* write address channel */
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// validates the address on the bus
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output axi_awvalid
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// write address ID, this signal is the identification tag for the write address group of signals
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output [ 3:0] axi_awid
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// burst type, this must use INCR (incrementing address burst) -- 2'b01
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output [ 1:0] axi_awburst
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// lock type, atomic characteristics of the transfer -- must be set to 1'b0
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output axi_awlock
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// indicates the bufferable, cacheable, write-through, write-back, and allocate attributes -- 4'b0011 recommended by Xilinx, IP as slaves in general ignores
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output [ 3:0] axi_awcache
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// protection type -- not used in the core, recommended value 3'b000
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output [ 2:0] axi_awprot
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// not implemented in Xilinx Endpoint IP
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output [ 3:0] axi_awqos
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// not implemented in Xilinx Endpoint IP
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output [ 3:0] axi_awuser
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// up to 256 beats for incrementing (INCR)
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output [ 7:0] axi_awlen
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// transfer width 8 to 1024 supported, in general the MIG core has 512 bits interface
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output [ 2:0] axi_awsize
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// write address
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output [ 31:0] axi_awaddr
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// write ready, indicates that the slave can accept the address
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input axi_awready
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/* write data channel */
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// validate the data on the bus
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output axi_wvalid
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// write data
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output [AXI_DATA_WIDTH-1:0] axi_wdata
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/8)-1:0] axi_wstrb // write strobe, indicates which byte lanes to update
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output [(AXI_DATA_WIDTH
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// fully supported, this signal indicates the last transfer in a write burst
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output axi_wlast
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// not implemented in Xilinx Endpoint IP
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output [ 3:0] axi_wuser
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// write ready, indicates that the slave can accept the data
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input axi_wready
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/* write response channel */
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// validates the write response of the slave
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input axi_bvalid
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// the identification tag of the write response, the BID value must match the AWID
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input [ 3:0] axi_bid
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// write response, indicate the status of the transfer
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input [ 1:0] axi_bresp
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// not implemented in Xilinx Endpoint IP
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input [ 3:0] axi_buser
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// response ready, indicates that the master can accept the data
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output axi_bready
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/* read address channel */
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// validates the address on the bus
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output axi_arvalid
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// read address ID, this signal is the identification tag for the read address group of signals
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output [ 3:0] axi_arid
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// burst type, this must use INCR (incrementing address burst) -- 2'b01
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output [ 1:0] axi_arburst
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// lock type, atomic characteristics of the transfer -- must be set to 1'b0
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output axi_arlock
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// indicates the bufferable, cacheable, write-through, write-back, and allocate attributes -- 4'b0011 recommended by Xilinx, IP as slaves in general ignores
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output [ 3:0] axi_arcache
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// protection type -- not used in the core
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output [ 2:0] axi_arprot
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// not implemented in Xilinx Endpoint IP
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output [ 3:0] axi_arqos
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// not implemented in Xilinx Endpoint IP
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output [ 3:0] axi_aruser
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// up to 256 beats for incrementing (INCR)
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output [ 7:0] axi_arlen
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// transfer width 8 to 1024 supported, in general the MIG core has 512 bits interface
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output [ 2:0] axi_arsize
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// read address
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output [ 31:0] axi_araddr
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// read ready, indicates that the slave can accept the address
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input axi_arready
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/* read data channel */
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// validate the data on the bus
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input axi_rvalid
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// the RID is generated by the slave and must match by the ARID value
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input [ 3:0] axi_rid
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// not implemented in Xilinx Endpoint IP
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input [ 3:0] axi_ruser
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// read response, indicate the status of the transfer
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input [ 1:0] axi_rresp
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// indicates the last transfer in a read burst
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input axi_rlast
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// read data drivers by the slave
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input [AXI_DATA_WIDTH-1:0] axi_rdata
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// read ready, indicates that the master can accept the data
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output axi_rready
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```
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### Avalon Memory Mapped master (AVL_MM)
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An Avalon Memory Mapped interface which transfer data into/from an external DDR4
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memory. This interface will be used explicitly with Intel FPGAs.
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```verilog
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// interface clock and reset
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input avl_clk
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input avl_reset
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// address for read or write
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output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address
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// indicate the number of transfers in each burst
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output reg [ 6:0] avl_burstcount
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// enables specific byte lanes during transfers on interfaces fo width greater than 8 bits [3]
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output reg [ 63:0] avl_byteenable
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// asserted to indicate a read transfer (request)
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output avl_read
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// read data, driven from the slave to the master
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input [(AVL_DATA_WIDTH-1):0] avl_readdata
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// used for variable-latency, pipelined read transfers, to validate the data on the bus
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input avl_readdata_valid
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// or waitrequest_n in specs, indicates the availability of the slave
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input avl_ready
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// asserted to indicate a write transfer
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output avl_write
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// write data, driven from the master to the slave
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output [(AVL_DATA_WIDTH-1):0] avl_writedata
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```
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### Initialization request interface
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Define a simple request/acknowledge interface to initialize the memory:
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@ -611,11 +425,11 @@ the AXI stream interface)
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### RX control FSM for internal RAM mode
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### TX control FSM for internal RAM mode
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**TODO** FSMs for the external DDR mode
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@ -1,6 +1,4 @@
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x="607.05249"
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y="724.40942"
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style="text-align:center;text-anchor:middle" /><tspan
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sodipodi:role="line"
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x="607.05249"
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y="751.07605"
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style="text-align:center;text-anchor:middle">DESTINATION</tspan></text>
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d="m 340.42141,914.39756 v 37.14286"
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id="path8360-3"
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inkscape:connector-curvature="0"
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sodipodi:nodetypes="cc" />
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<path
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style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.5;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker8368-5-6)"
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d="M 443.45697,962.08331 V 924.94045"
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xml:space="preserve"
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x="304.78723"
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y="907.06915"
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style="font-size:15px;line-height:1.25">FIFO_WR</tspan></text>
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<text
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xml:space="preserve"
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style="font-style:normal;font-weight:normal;line-height:0%;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
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id="rect4733-3-2"
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x="312.84314"
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y="963.01801" />
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<text
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xml:space="preserve"
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style="font-style:normal;font-weight:normal;line-height:0%;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1"
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x="342.2413"
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transform="scale(0.99083586,1.0092489)"><tspan
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sodipodi:role="line"
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x="342.2413"
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style="font-size:17.5px;line-height:1.25">Storage Unit</tspan></text>
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</svg>
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|
|
|
|||
|
Before Width: | Height: | Size: 33 KiB After Width: | Height: | Size: 21 KiB |
Loading…
Reference in New Issue