axi_clkgen: add ultrascale series support

library/axi_clkgen/axi_clkgen.v

@@ -142,7 +142,9 @@ module axi_clkgen #(
 
   // processor interface
 
-  up_clkgen i_up_clkgen (
+  up_clkgen #(
+    .ID(ID)
+  ) i_up_clkgen (
     .mmcm_rst (mmcm_rst),
     .clk_sel (clk_sel),
     .up_drp_sel (up_drp_sel_s),

library/xilinx/common/ad_mmcm_drp.v

@@ -74,6 +74,7 @@ module ad_mmcm_drp #(
 
   localparam  MMCM_DEVICE_7SERIES = 0;
   localparam  MMCM_DEVICE_VIRTEX6 = 1;
+  localparam  MMCM_DEVICE_ULTRASCALE = 2;
 
 
   // internal registers
@@ -175,7 +176,75 @@ module ad_mmcm_drp #(
       BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
       BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
 
-  end else begin /* MMCM_DEVICE_TYPE == 1 */
+  end else if (MMCM_DEVICE_TYPE == MMCM_DEVICE_ULTRASCALE) begin
+    MMCME3_ADV #(
+      .BANDWIDTH ("OPTIMIZED"),
+      .CLKOUT4_CASCADE ("FALSE"),
+      .COMPENSATION ("AUTO"),
+      .STARTUP_WAIT ("FALSE"),
+
+      .DIVCLK_DIVIDE (MMCM_VCO_DIV),
+      .CLKFBOUT_MULT_F (MMCM_VCO_MUL),
+      .CLKFBOUT_PHASE (0.000),
+      .CLKFBOUT_USE_FINE_PS ("FALSE"),
+      .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
+      .CLKOUT0_PHASE (MMCM_CLK0_PHASE),
+      .CLKOUT0_DUTY_CYCLE (0.500),
+      .CLKOUT0_USE_FINE_PS ("FALSE"),
+      .CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
+      .CLKOUT1_PHASE (MMCM_CLK1_PHASE),
+      .CLKOUT1_DUTY_CYCLE (0.500),
+      .CLKOUT1_USE_FINE_PS ("FALSE"),
+      .CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
+      .CLKOUT2_PHASE (MMCM_CLK2_PHASE),
+      .CLKOUT2_DUTY_CYCLE (0.500),
+      .CLKOUT2_USE_FINE_PS ("FALSE"),
+      .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
+      .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
+      .REF_JITTER1 (0.010))
+    i_mmcme3 (
+      .CLKIN1 (clk),
+      .CLKFBIN (bufg_fb_clk_s),
+      .CLKFBOUT (mmcm_fb_clk_s),
+      .CLKOUT0 (mmcm_clk_0_s),
+      .CLKOUT1 (mmcm_clk_1_s),
+      .CLKOUT2 (mmcm_clk_2_s),
+      .LOCKED (mmcm_locked_s),
+      .DCLK (up_clk),
+      .DEN (up_drp_sel),
+      .DADDR (up_drp_addr[6:0]),
+      .DWE (up_drp_wr),
+      .DI (up_drp_wdata),
+      .DO (up_drp_rdata_s),
+      .DRDY (up_drp_ready_s),
+      .CLKFBOUTB (),
+      .CLKOUT0B (),
+      .CLKOUT1B (),
+      .CLKOUT2B (),
+      .CLKOUT3 (),
+      .CLKOUT3B (),
+      .CLKOUT4 (),
+      .CLKOUT5 (),
+      .CLKOUT6 (),
+      .CLKIN2 (clk2),
+      .CLKINSEL (clk_sel),
+      .PSCLK (1'b0),
+      .PSEN (1'b0),
+      .PSINCDEC (1'b0),
+      .PSDONE (),
+      .CLKINSTOPPED (),
+      .CLKFBSTOPPED (),
+      .PWRDWN (1'b0),
+      .CDDCREQ (1'b0),
+      .CDDCDONE (),
+      .RST (mmcm_rst));
+
+      BUFG i_fb_clk_bufg  (.I (mmcm_fb_clk_s),  .O (bufg_fb_clk_s));
+      BUFG i_clk_0_bufg   (.I (mmcm_clk_0_s),   .O (mmcm_clk_0));
+      BUFG i_clk_1_bufg   (.I (mmcm_clk_1_s),   .O (mmcm_clk_1));
+      BUFG i_clk_2_bufg   (.I (mmcm_clk_2_s),   .O (mmcm_clk_2));
+
+  end else if (MMCM_DEVICE_TYPE == MMCM_DEVICE_VIRTEX6) begin 
 
     MMCM_ADV #(
       .BANDWIDTH ("OPTIMIZED"),