diff --git a/library/axi_ad9361/axi_ad9361_rx_channel.v b/library/axi_ad9361/axi_ad9361_rx_channel.v
index 4cb877cd0..197ebf967 100644
--- a/library/axi_ad9361/axi_ad9361_rx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_rx_channel.v
@@ -122,8 +122,7 @@ module axi_ad9361_rx_channel (
   wire            adc_dfmt_valid_s;
   wire    [15:0]  adc_dfmt_data_s;
   wire            adc_dcfilter_valid_s;
-  wire    [15:0]  adc_dcfilter_data_i_s;
-  wire    [15:0]  adc_dcfilter_data_q_s;
+  wire    [15:0]  adc_dcfilter_data_s;
   wire            adc_iqcor_enb_s;
   wire            adc_dcfilt_enb_s;
   wire            adc_dfmt_se_s;
@@ -141,8 +140,7 @@ module axi_ad9361_rx_channel (
   // iq correction inputs
 
   assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data;
-  assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in  : adc_dcfilter_data_out;
-  assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in;
+  assign adc_dcfilter_data_out = adc_dcfilter_data_s;
 
   axi_ad9361_rx_pnmon #(.IQSEL (IQSEL), .PRBS_SEL (CHID)) i_rx_pnmon (
     .adc_clk (adc_clk),
@@ -173,14 +171,14 @@ module axi_ad9361_rx_channel (
   generate
   if (DP_DISABLE == 1) begin
   assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
-  assign adc_dcfilter_data_out = adc_dfmt_data_s;
+  assign adc_dcfilter_data_s = adc_dfmt_data_s;
   end else begin
   ad_dcfilter i_ad_dcfilter (
     .clk (adc_clk),
     .valid (adc_dfmt_valid_s),
     .data (adc_dfmt_data_s),
     .valid_out (adc_dcfilter_valid_s),
-    .data_out (adc_dcfilter_data_out),
+    .data_out (adc_dcfilter_data_s),
     .dcfilt_enb (adc_dcfilt_enb_s),
     .dcfilt_coeff (adc_dcfilt_coeff_s),
     .dcfilt_offset (adc_dcfilt_offset_s));
@@ -190,13 +188,13 @@ module axi_ad9361_rx_channel (
   generate
   if (DP_DISABLE == 1) begin
   assign adc_iqcor_valid = adc_dcfilter_valid_s;
-  assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s;
+  assign adc_iqcor_data = adc_dcfilter_data_s;
   end else begin
   ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor (
     .clk (adc_clk),
     .valid (adc_dcfilter_valid_s),
-    .data_i (adc_dcfilter_data_i_s),
-    .data_q (adc_dcfilter_data_q_s),
+    .data_in (adc_dcfilter_data_s),
+    .data_iq (adc_dcfilter_data_in),
     .valid_out (adc_iqcor_valid),
     .data_out (adc_iqcor_data),
     .iqcor_enable (adc_iqcor_enb_s),
diff --git a/library/axi_ad9361/axi_ad9361_tx_channel.v b/library/axi_ad9361/axi_ad9361_tx_channel.v
index 581915d94..e424595fd 100644
--- a/library/axi_ad9361/axi_ad9361_tx_channel.v
+++ b/library/axi_ad9361/axi_ad9361_tx_channel.v
@@ -129,8 +129,6 @@ module axi_ad9361_tx_channel (
 
   // internal signals
 
-  wire    [11:0]  dac_data_i_s;
-  wire    [11:0]  dac_data_q_s;
   wire            dac_iqcor_valid_s;
   wire    [15:0]  dac_iqcor_data_s;
   wire    [15:0]  dac_dds_data_s;
@@ -275,9 +273,6 @@ module axi_ad9361_tx_channel (
 
   // dac iq correction
 
-  assign dac_data_i_s = (IQSEL == 1) ? dac_data_in  : dac_data_out;
-  assign dac_data_q_s = (IQSEL == 1) ? dac_data_out : dac_data_in;
-
   always @(posedge dac_clk) begin
     dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
     if (dac_iqcor_valid_s == 1'b1) begin
@@ -293,8 +288,8 @@ module axi_ad9361_tx_channel (
   ad_iqcor #(.IQSEL (IQSEL)) i_ad_iqcor (
     .clk (dac_clk),
     .valid (dac_valid),
-    .data_i ({dac_data_i_s, 4'd0}),
-    .data_q ({dac_data_q_s, 4'd0}),
+    .data_in ({dac_data_out, 4'd0}),
+    .data_iq ({dac_data_in, 4'd0}),
     .valid_out (dac_iqcor_valid_s),
     .data_out (dac_iqcor_data_s),
     .iqcor_enable (dac_iqcor_enb_s),