diff --git a/projects/ad9083_evb/a10soc/Makefile b/projects/ad9083_evb/a10soc/Makefile new file mode 100644 index 000000000..c763e7c7f --- /dev/null +++ b/projects/ad9083_evb/a10soc/Makefile @@ -0,0 +1,25 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9083_evb_a10soc + +M_DEPS += ../common/ad9083_evb_qsys.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/intel/adcfifo_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_qsys.tcl +M_DEPS += ../../common/a10soc/a10soc_system_assign.tcl +M_DEPS += ../../common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += intel/adi_jesd204 +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_pack/util_cpack2 + +include ../../scripts/project-intel.mk diff --git a/projects/ad9083_evb/a10soc/system_constr.sdc b/projects/ad9083_evb/a10soc/system_constr.sdc new file mode 100644 index 000000000..433dfe927 --- /dev/null +++ b/projects/ad9083_evb/a10soc/system_constr.sdc @@ -0,0 +1,9 @@ + +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "8.000 ns" -name rx_device_clk [get_ports {rx_device_clk}] +create_clock -period "2.000 ns" -name rx_ref_clk [get_ports {rx_ref_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/ad9083_evb/a10soc/system_project.tcl b/projects/ad9083_evb/a10soc/system_project.tcl new file mode 100644 index 000000000..22b688490 --- /dev/null +++ b/projects/ad9083_evb/a10soc/system_project.tcl @@ -0,0 +1,82 @@ + +source ../../scripts/adi_env.tcl +source ../../scripts/adi_project_intel.tcl + +adi_project ad9083_evb_a10soc + +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_assign.tcl + +# files + +set_global_assignment -name VERILOG_FILE ../../../library/common/ad_3w_spi.v + +# lane interface + +# Note: This projects requires a hardware rework to function correctly. +# The rework connects FMC header pins directly to the FPGA so that they can be +# accessed by the fabric. +# +# Changes required: +# R610: DNI -> R0 +# R611: DNI -> R0 +# R612: R0 -> DNI +# R613: R0 -> DNI +# R620: DNI -> R0 +# R632: DNI -> R0 +# R621: R0 -> DNI +# R633: R0 -> DNI + +set_location_assignment PIN_G14 -to rx_device_clk ; ## G06 FMCA_HPC_LA00_CC_P +set_location_assignment PIN_H14 -to "rx_device_clk(n)" ; ## G07 FMCA_HPC_LA00_CC_N + +set_location_assignment PIN_N29 -to rx_ref_clk ; ## D04 FMCA_HPC_GBTCLK0_M2C_P +set_location_assignment PIN_N28 -to "rx_ref_clk(n)" ; ## D05 FMCA_HPC_GBTCLK0_M2C_N + +set_location_assignment PIN_T31 -to rx_serial_data[0] ; ## C06 FMCA_HPC_DP0_M2C_P +set_location_assignment PIN_T30 -to "rx_serial_data[0](n)" ; ## C07 FMCA_HPC_DP0_M2C_N +set_location_assignment PIN_R33 -to rx_serial_data[1] ; ## A02 FMCA_HPC_DP1_M2C_P +set_location_assignment PIN_R32 -to "rx_serial_data[1](n)" ; ## A03 FMCA_HPC_DP1_M2C_N +set_location_assignment PIN_P35 -to rx_serial_data[2] ; ## A06 FMCA_HPC_DP2_M2C_P +set_location_assignment PIN_P34 -to "rx_serial_data[2](n)" ; ## A07 FMCA_HPC_DP2_M2C_N +set_location_assignment PIN_P31 -to rx_serial_data[3] ; ## A10 FMCA_HPC_DP3_M2C_P +set_location_assignment PIN_P30 -to "rx_serial_data[3](n)" ; ## A11 FMCA_HPC_DP3_M2C_N + +set_location_assignment PIN_H12 -to rx_sync ; ## H10 FMCA_HPC_LA04_P +set_location_assignment PIN_H13 -to "rx_sync(n)" ; ## H11 FMCA_HPC_LA04_N +set_location_assignment PIN_B11 -to rx_sysref ; ## G12 FMCA_HPC_LA08_P +set_location_assignment PIN_B12 -to "rx_sysref(n)" ; ## G13 FMCA_HPC_LA08_N + +set_instance_assignment -name IO_STANDARD LVDS -to rx_device_clk +set_instance_assignment -name IO_STANDARD LVDS -to "rx_device_clk(n)" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_device_clk +set_instance_assignment -name IO_STANDARD LVDS -to rx_ref_clk +set_instance_assignment -name IO_STANDARD LVDS -to "rx_ref_clk(n)" +set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_serial_data +set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_serial_data +set_instance_assignment -name IO_STANDARD LVDS -to rx_sync +set_instance_assignment -name IO_STANDARD LVDS -to "rx_sync(n)" +set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref +set_instance_assignment -name IO_STANDARD LVDS -to "rx_sysref(n)" +set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref + +set_location_assignment PIN_D13 -to pwdn ; ## H08 FMCA_HPC_LA02_N +set_location_assignment PIN_A9 -to rstb ; ## H13 FMCA_HPC_LA07_P +set_location_assignment PIN_C14 -to refsel ; ## G09 FMCA_HPC_LA03_P + +set_instance_assignment -name IO_STANDARD "1.8 V" -to pwdn +set_instance_assignment -name IO_STANDARD "1.8 V" -to rstb +set_instance_assignment -name IO_STANDARD "1.8 V" -to refsel + +# spi + +set_location_assignment PIN_B9 -to spi_csn_clk ; ## H14 FMCA_LA07_N +set_location_assignment PIN_C13 -to spi_csn_adc ; ## H07 FMCA_LA02_P +set_location_assignment PIN_E12 -to spi_clk ; ## D08 FMCA_LA01_P_CC +set_location_assignment PIN_E13 -to spi_sdio ; ## D09 FMCA_LA01_N_CC + +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_csn_adc +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_clk +set_instance_assignment -name IO_STANDARD "1.8 V" -to spi_sdio + +execute_flow -compile diff --git a/projects/ad9083_evb/a10soc/system_qsys.tcl b/projects/ad9083_evb/a10soc/system_qsys.tcl new file mode 100644 index 000000000..33d6a00b4 --- /dev/null +++ b/projects/ad9083_evb/a10soc/system_qsys.tcl @@ -0,0 +1,17 @@ + +set adc_fifo_address_width 8 + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_system_qsys.tcl +source $ad_hdl_dir/projects/common/a10soc/a10soc_plddr4_dacfifo_qsys.tcl +source $ad_hdl_dir/projects/common/intel/adcfifo_qsys.tcl +source ../common/ad9083_evb_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +sysid_gen_sys_init_file; + diff --git a/projects/ad9083_evb/a10soc/system_top.v b/projects/ad9083_evb/a10soc/system_top.v new file mode 100644 index 000000000..0601a3a66 --- /dev/null +++ b/projects/ad9083_evb/a10soc/system_top.v @@ -0,0 +1,264 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + // clock and resets + + input sys_clk, + input sys_resetn, + + // hps-ddr4 (32) + + input hps_ddr_ref_clk, + output [ 0:0] hps_ddr_clk_p, + output [ 0:0] hps_ddr_clk_n, + output [ 16:0] hps_ddr_a, + output [ 1:0] hps_ddr_ba, + output [ 0:0] hps_ddr_bg, + output [ 0:0] hps_ddr_cke, + output [ 0:0] hps_ddr_cs_n, + output [ 0:0] hps_ddr_odt, + output [ 0:0] hps_ddr_reset_n, + output [ 0:0] hps_ddr_act_n, + output [ 0:0] hps_ddr_par, + input [ 0:0] hps_ddr_alert_n, + inout [ 3:0] hps_ddr_dqs_p, + inout [ 3:0] hps_ddr_dqs_n, + inout [ 31:0] hps_ddr_dq, + inout [ 3:0] hps_ddr_dbi_n, + input hps_ddr_rzq, + + // hps-ethernet + + input [ 0:0] hps_eth_rxclk, + input [ 0:0] hps_eth_rxctl, + input [ 3:0] hps_eth_rxd, + output [ 0:0] hps_eth_txclk, + output [ 0:0] hps_eth_txctl, + output [ 3:0] hps_eth_txd, + output [ 0:0] hps_eth_mdc, + inout [ 0:0] hps_eth_mdio, + + // hps-sdio + + output [ 0:0] hps_sdio_clk, + inout [ 0:0] hps_sdio_cmd, + inout [ 7:0] hps_sdio_d, + + // hps-usb + + input [ 0:0] hps_usb_clk, + input [ 0:0] hps_usb_dir, + input [ 0:0] hps_usb_nxt, + output [ 0:0] hps_usb_stp, + inout [ 7:0] hps_usb_d, + + // hps-uart + + input [ 0:0] hps_uart_rx, + output [ 0:0] hps_uart_tx, + + // hps-i2c (shared w fmc-a, fmc-b) + + inout [ 0:0] hps_i2c_sda, + inout [ 0:0] hps_i2c_scl, + + // hps-gpio (max-v-u16) + + inout [ 3:0] hps_gpio, + + // gpio (max-v-u21) + + input [ 7:0] gpio_bd_i, + output [ 3:0] gpio_bd_o, + + // link interface + + input rx_device_clk, + input rx_ref_clk, + input rx_sysref, + output rx_sync, + input [ 3:0] rx_serial_data, + + // gpio + + output pwdn, + output rstb, + output refsel, + + // spi + + output spi_csn_clk, + output spi_csn_adc, + output spi_clk, + inout spi_sdio); + + // internal signals + + wire sys_hps_resetn; + wire sys_resetn_s; + wire [ 63:0] gpio_i; + wire [ 63:0] gpio_o; + wire spi_miso_s; + wire spi_mosi_s; + wire [ 7:0] spi_csn_s; + + // assignments + + assign spi_csn_adc = spi_csn_s[0]; + assign spi_csn_clk = spi_csn_s[1]; + + ad_3w_spi #( + .NUM_OF_SLAVES(2)) + i_spi ( + .spi_csn (spi_csn_s[1:0]), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi_s), + .spi_miso (spi_miso_s), + .spi_sdio (spi_sdio), + .spi_dir () + ); + + // gpio in & out are separate cores + + assign gpio_i[63:32] = gpio_o[63:32]; + assign refsel = gpio_o[34]; + assign rstb = gpio_o[33]; + assign pwdn = gpio_o[32]; + + // board stuff (max-v-u21) + + assign gpio_i[31:12] = gpio_o[31:12]; + assign gpio_i[11: 4] = gpio_bd_i; + assign gpio_i[ 3: 0] = gpio_o[ 3: 0]; + + assign gpio_bd_o = gpio_o[3:0]; + + // peripheral reset + + assign sys_resetn_s = sys_resetn & sys_hps_resetn; + + // instantiations + + system_bd i_system_bd ( + .rx_ref_clk_clk (rx_ref_clk), + .rx_serial_data_rx_serial_data (rx_serial_data), + .rx_sysref_export (rx_sysref), + .rx_sync_export (rx_sync), + .pr_rom_data_nc_rom_data('h0), + .rx_device_clk_clk (rx_device_clk), + .sys_clk_clk (sys_clk), + .sys_rstn_reset_n (sys_resetn_s), + .sys_gpio_bd_in_port (gpio_i[31:0]), + .sys_gpio_bd_out_port (gpio_o[31:0]), + .sys_gpio_in_export (gpio_i[63:32]), + .sys_gpio_out_export (gpio_o[63:32]), + .sys_hps_rstn_reset_n (sys_resetn), + .sys_hps_io_hps_io_phery_emac0_TX_CLK (hps_eth_txclk), + .sys_hps_io_hps_io_phery_emac0_TXD0 (hps_eth_txd[0]), + .sys_hps_io_hps_io_phery_emac0_TXD1 (hps_eth_txd[1]), + .sys_hps_io_hps_io_phery_emac0_TXD2 (hps_eth_txd[2]), + .sys_hps_io_hps_io_phery_emac0_TXD3 (hps_eth_txd[3]), + .sys_hps_io_hps_io_phery_emac0_RX_CTL (hps_eth_rxctl), + .sys_hps_io_hps_io_phery_emac0_TX_CTL (hps_eth_txctl), + .sys_hps_io_hps_io_phery_emac0_RX_CLK (hps_eth_rxclk), + .sys_hps_io_hps_io_phery_emac0_RXD0 (hps_eth_rxd[0]), + .sys_hps_io_hps_io_phery_emac0_RXD1 (hps_eth_rxd[1]), + .sys_hps_io_hps_io_phery_emac0_RXD2 (hps_eth_rxd[2]), + .sys_hps_io_hps_io_phery_emac0_RXD3 (hps_eth_rxd[3]), + .sys_hps_io_hps_io_phery_emac0_MDIO (hps_eth_mdio), + .sys_hps_io_hps_io_phery_emac0_MDC (hps_eth_mdc), + .sys_hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_cmd), + .sys_hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_d[0]), + .sys_hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_d[1]), + .sys_hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_d[2]), + .sys_hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_d[3]), + .sys_hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_d[4]), + .sys_hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_d[5]), + .sys_hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_d[6]), + .sys_hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_d[7]), + .sys_hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_clk), + .sys_hps_io_hps_io_phery_usb0_DATA0 (hps_usb_d[0]), + .sys_hps_io_hps_io_phery_usb0_DATA1 (hps_usb_d[1]), + .sys_hps_io_hps_io_phery_usb0_DATA2 (hps_usb_d[2]), + .sys_hps_io_hps_io_phery_usb0_DATA3 (hps_usb_d[3]), + .sys_hps_io_hps_io_phery_usb0_DATA4 (hps_usb_d[4]), + .sys_hps_io_hps_io_phery_usb0_DATA5 (hps_usb_d[5]), + .sys_hps_io_hps_io_phery_usb0_DATA6 (hps_usb_d[6]), + .sys_hps_io_hps_io_phery_usb0_DATA7 (hps_usb_d[7]), + .sys_hps_io_hps_io_phery_usb0_CLK (hps_usb_clk), + .sys_hps_io_hps_io_phery_usb0_STP (hps_usb_stp), + .sys_hps_io_hps_io_phery_usb0_DIR (hps_usb_dir), + .sys_hps_io_hps_io_phery_usb0_NXT (hps_usb_nxt), + .sys_hps_io_hps_io_phery_uart1_RX (hps_uart_rx), + .sys_hps_io_hps_io_phery_uart1_TX (hps_uart_tx), + .sys_hps_io_hps_io_phery_i2c1_SDA (hps_i2c_sda), + .sys_hps_io_hps_io_phery_i2c1_SCL (hps_i2c_scl), + .sys_hps_io_hps_io_gpio_gpio1_io5 (hps_gpio[0]), + .sys_hps_io_hps_io_gpio_gpio1_io14 (hps_gpio[1]), + .sys_hps_io_hps_io_gpio_gpio1_io16 (hps_gpio[2]), + .sys_hps_io_hps_io_gpio_gpio1_io17 (hps_gpio[3]), + .sys_hps_out_rstn_reset_n (sys_hps_resetn), + .sys_hps_ddr_rstn_reset_n (sys_resetn), + .sys_hps_ddr_ref_clk_clk (hps_ddr_ref_clk), + .sys_hps_ddr_oct_oct_rzqin (hps_ddr_rzq), + .sys_hps_ddr_mem_ck (hps_ddr_clk_p), + .sys_hps_ddr_mem_ck_n (hps_ddr_clk_n), + .sys_hps_ddr_mem_a (hps_ddr_a), + .sys_hps_ddr_mem_act_n (hps_ddr_act_n), + .sys_hps_ddr_mem_ba (hps_ddr_ba), + .sys_hps_ddr_mem_bg (hps_ddr_bg), + .sys_hps_ddr_mem_cke (hps_ddr_cke), + .sys_hps_ddr_mem_cs_n (hps_ddr_cs_n), + .sys_hps_ddr_mem_odt (hps_ddr_odt), + .sys_hps_ddr_mem_reset_n (hps_ddr_reset_n), + .sys_hps_ddr_mem_par (hps_ddr_par), + .sys_hps_ddr_mem_alert_n (hps_ddr_alert_n), + .sys_hps_ddr_mem_dqs (hps_ddr_dqs_p), + .sys_hps_ddr_mem_dqs_n (hps_ddr_dqs_n), + .sys_hps_ddr_mem_dq (hps_ddr_dq), + .sys_hps_ddr_mem_dbi_n (hps_ddr_dbi_n), + .sys_spi_MISO (spi_miso_s), + .sys_spi_MOSI (spi_mosi_s), + .sys_spi_SCLK (spi_clk), + .sys_spi_SS_n (spi_csn_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/ad9083_evb/common/ad9083_evb_qsys.tcl b/projects/ad9083_evb/common/ad9083_evb_qsys.tcl new file mode 100644 index 000000000..36d187acd --- /dev/null +++ b/projects/ad9083_evb/common/ad9083_evb_qsys.tcl @@ -0,0 +1,150 @@ +# JESD204B attributes + +set RX_NUM_OF_LANES 4 ; # L +set RX_NUM_OF_CONVERTERS 16 ; # M +set RX_SAMPLES_PER_FRAME 1 ; # S +set RX_SAMPLE_WIDTH 16 ; # N/NP + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 64 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] + +set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL] + +# +## IP instantiations and configuration +# + +add_instance device_clk altera_clock_bridge +set_instance_parameter_value device_clk {EXPLICIT_CLOCK_RATE} {125000000} + +# ad9083_jesd204 JESD204B phy-link layer + +add_instance ad9083_jesd204 adi_jesd204 +set_instance_parameter_value ad9083_jesd204 {ID} {0} +set_instance_parameter_value ad9083_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9083_jesd204 {SOFT_PCS} {true} +set_instance_parameter_value ad9083_jesd204 {LANE_RATE} {10000.0} +set_instance_parameter_value ad9083_jesd204 {SYSCLK_FREQUENCY} {100.0} +set_instance_parameter_value ad9083_jesd204 {REFCLK_FREQUENCY} {500.0} +set_instance_parameter_value ad9083_jesd204 {INPUT_PIPELINE_STAGES} {2} +set_instance_parameter_value ad9083_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value ad9083_jesd204 {EXT_DEVICE_CLK_EN} {1} +set_instance_parameter_value ad9083_jesd204 {TPL_DATA_PATH_WIDTH} {8} + +add_connection sys_clk.clk ad9083_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9083_jesd204.sys_resetn +add_connection device_clk.out_clk ad9083_jesd204.device_clk + +# ad9083_tpl_0 JESD204B transport layer + +add_instance axi_ad9083 ad_ip_jesd204_tpl_adc +set_instance_parameter_value axi_ad9083 {ID} {0} +set_instance_parameter_value axi_ad9083 {NUM_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value axi_ad9083 {NUM_LANES} $RX_NUM_OF_LANES +set_instance_parameter_value axi_ad9083 {BITS_PER_SAMPLE} $RX_SAMPLE_WIDTH +set_instance_parameter_value axi_ad9083 {CONVERTER_RESOLUTION} $RX_SAMPLE_WIDTH +set_instance_parameter_value axi_ad9083 {TWOS_COMPLEMENT} {1} +set_instance_parameter_value axi_ad9083 {OCTETS_PER_BEAT} {8} + +add_connection ad9083_jesd204.link_sof axi_ad9083.if_link_sof +add_connection ad9083_jesd204.link_data axi_ad9083.link_data +add_connection sys_clk.clk_reset axi_ad9083.s_axi_reset +add_connection sys_clk.clk axi_ad9083.s_axi_clock + +# ad9083-pack + +add_instance util_ad9083_cpack util_cpack2 +set_instance_parameter_value util_ad9083_cpack {NUM_OF_CHANNELS} $RX_NUM_OF_CONVERTERS +set_instance_parameter_value util_ad9083_cpack {SAMPLES_PER_CHANNEL} $RX_SAMPLES_PER_FRAME +set_instance_parameter_value util_ad9083_cpack {SAMPLE_DATA_WIDTH} $RX_SAMPLE_WIDTH + +add_connection ad9083_jesd204.link_reset util_ad9083_cpack.reset +add_connection device_clk.out_clk util_ad9083_cpack.clk + +for {set i 0} {$i< $RX_NUM_OF_CONVERTERS} {incr i} { + add_connection axi_ad9083.adc_ch_${i} util_ad9083_cpack.adc_ch_${i} +} + +# ADC FIFO's + +add_instance ad9083_adcfifo util_adcfifo +set_instance_parameter_value ad9083_adcfifo {ADC_DATA_WIDTH} $adc_data_width +set_instance_parameter_value ad9083_adcfifo {DMA_DATA_WIDTH} $adc_data_width +set_instance_parameter_value ad9083_adcfifo {DMA_ADDRESS_WIDTH} {16} + +add_connection sys_clk.clk_reset ad9083_adcfifo.if_adc_rst +add_connection device_clk.out_clk ad9083_adcfifo.if_adc_clk +add_connection util_ad9083_cpack.if_packed_fifo_wr_en ad9083_adcfifo.if_adc_wr +add_connection util_ad9083_cpack.if_packed_fifo_wr_data ad9083_adcfifo.if_adc_wdata +add_connection sys_dma_clk.clk ad9083_adcfifo.if_dma_clk +add_connection sys_dma_clk.clk_reset ad9083_adcfifo.if_adc_rst + +# DMA instances + +add_instance axi_ad9083_dma axi_dmac +set_instance_parameter_value axi_ad9083_dma {ID} {0} +set_instance_parameter_value axi_ad9083_dma {DMA_DATA_WIDTH_SRC} $adc_data_width +set_instance_parameter_value axi_ad9083_dma {DMA_DATA_WIDTH_DEST} {128} +set_instance_parameter_value axi_ad9083_dma {DMA_LENGTH_WIDTH} {24} +set_instance_parameter_value axi_ad9083_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_ad9083_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_ad9083_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_ad9083_dma {SYNC_TRANSFER_START} {0} +set_instance_parameter_value axi_ad9083_dma {CYCLIC} {0} +set_instance_parameter_value axi_ad9083_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_ad9083_dma {DMA_TYPE_SRC} {1} +set_instance_parameter_value axi_ad9083_dma {DMA_AXI_PROTOCOL_DEST} {0} +set_instance_parameter_value axi_ad9083_dma {MAX_BYTES_PER_BURST} {128} +set_instance_parameter_value axi_ad9083_dma {FIFO_SIZE} {16} + +add_connection sys_clk.clk axi_ad9083_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_ad9083_dma.s_axi_reset +add_connection device_clk.out_clk axi_ad9083.link_clk +add_connection ad9083_adcfifo.m_axis axi_ad9083_dma.s_axis +add_connection ad9083_adcfifo.if_dma_xfer_req axi_ad9083_dma.if_s_axis_xfer_req +add_connection ad9083_adcfifo.if_adc_wovf axi_ad9083.if_adc_dovf +add_connection sys_dma_clk.clk axi_ad9083_dma.if_s_axis_aclk +add_connection sys_dma_clk.clk_reset axi_ad9083_dma.m_dest_axi_reset +add_connection sys_dma_clk.clk axi_ad9083_dma.m_dest_axi_clock + +# +## exported signals +# + +add_interface rx_ref_clk clock sink +add_interface rx_device_clk clock sink +add_interface rx_sysref conduit end +add_interface rx_sync conduit end +add_interface rx_serial_data conduit end + +set_interface_property rx_ref_clk EXPORT_OF ad9083_jesd204.ref_clk +set_interface_property rx_device_clk EXPORT_OF device_clk.in_clk +set_interface_property rx_sysref EXPORT_OF ad9083_jesd204.sysref +set_interface_property rx_sync EXPORT_OF ad9083_jesd204.sync +set_interface_property rx_serial_data EXPORT_OF ad9083_jesd204.serial_data + +# +## data interfaces / data path +# + +# addresses + +ad_cpu_interconnect 0x00040000 ad9083_jesd204.link_reconfig +ad_cpu_interconnect 0x00044000 ad9083_jesd204.link_management +ad_cpu_interconnect 0x00045000 ad9083_jesd204.link_pll_reconfig + +for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} { + ad_cpu_interconnect [expr 0x00048000 + $i * 0x1000] ad9083_jesd204.phy_reconfig_${i} +} + +ad_cpu_interconnect 0x0004c000 axi_ad9083_dma.s_axi +ad_cpu_interconnect 0x00050000 axi_ad9083.s_axi + +# dma interconnects +ad_dma_interconnect axi_ad9083_dma.m_dest_axi + +# +## interrupts +# + +ad_cpu_interrupt 11 ad9083_jesd204.interrupt +ad_cpu_interrupt 12 axi_ad9083_dma.interrupt_sender