zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

axi_dmac: Cleanup data mover 

With the recent rework there is now a fair amount of dead code in the
datamover module that is no longer used. Remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-05-24 15:33:21 +02:00 committed by Lars-Peter Clausen
parent 44e09f58cd
commit 62969bd7ab
3 changed files with 5 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
library/axi_dmac/data_mover.v
View File

@ -37,9 +37,7 @@ module dmac_data_mover #(
parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter DISABLE_WAIT_FOR_ID = 1,
parameter BEATS_PER_BURST_WIDTH = 4,
parameter LAST = 0)( /* 0 = last asserted at the end of each burst, 1 = last only asserted at the end of the transfer */
parameter BEATS_PER_BURST_WIDTH = 4) (
input clk,
input resetn,
@ -48,16 +46,12 @@ module dmac_data_mover #(
output [ID_WIDTH-1:0] response_id,
input eot,
input enable,
output reg enabled,
output xfer_req,
output s_axi_ready,
input s_axi_valid,
input [DATA_WIDTH-1:0] s_axi_data,
input m_axi_ready,
output m_axi_valid,
output [DATA_WIDTH-1:0] m_axi_data,
output m_axi_last,
@ -90,38 +84,16 @@ assign response_id = id;
assign last = eot ? last_eot : last_non_eot;
assign s_axi_ready = m_axi_ready & pending_burst & active;
assign s_axi_ready = pending_burst & active;
assign m_axi_valid = s_axi_valid & pending_burst & active;
assign m_axi_data = s_axi_data;
assign m_axi_last = LAST ? (last_eot & eot) : last;
assign m_axi_last = last;
// If we want to support zero delay between transfers we have to assert
// req_ready on the same cycle on which the last load happens.
assign last_load = s_axi_ready && s_axi_valid && last_eot && eot;
assign req_ready = last_load || ~active;
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable) begin
enabled <= 1'b1;
end else begin
if (DISABLE_WAIT_FOR_ID == 0) begin
// We are not allowed to just deassert valid, so wait until the
// current beat has been accepted
if (~s_axi_valid || m_axi_ready)
enabled <= 1'b0;
end else begin
// For memory mapped AXI busses we have to complete all pending
// burst requests before we can disable the data mover.
if (response_id == request_id)
enabled <= 1'b0;
end
end
end
end
always @(posedge clk) begin
if (req_ready) begin
last_eot <= req_last_burst_length == 'h0;

7
library/axi_dmac/src_axi_stream.v
View File

@ -78,6 +78,8 @@ wire has_sync = ~needs_sync | sync;
wire data_valid;
wire data_ready;
assign enabled = enable;
assign data = transfer_abort == 1'b1 ? {S_AXIS_DATA_WIDTH{1'b0}} : s_axis_data;
assign data_valid = (s_axis_valid & has_sync) | transfer_abort;
assign s_axis_ready = data_ready & ~transfer_abort;
@ -118,15 +120,11 @@ end
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(enabled),
.xfer_req(s_axis_xfer_req),
.request_id(request_id),
@ -140,7 +138,6 @@ dmac_data_mover # (
.s_axi_ready(data_ready),
.s_axi_valid(data_valid),
.s_axi_data(data),
.m_axi_ready(1'b1),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last)

5
library/axi_dmac/src_fifo_inf.v
View File

@ -94,15 +94,11 @@ end
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(),
.xfer_req(xfer_req),
.request_id(request_id),
@ -116,7 +112,6 @@ dmac_data_mover # (
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(din),
.m_axi_ready(1'b1),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last(fifo_last)