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util_clkdiv: Make the clock division parametrizable and changed C_SIM_DEVICE to SIM_DEVICE

main
Adrian Costina 2017-01-16 14:35:42 +02:00
parent b622b6592e
commit 61ee24f26a
4 changed files with 34 additions and 25 deletions
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1
library/util_clkdiv/Makefile
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@ -8,6 +8,7 @@
M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_clkdiv.v
M_DEPS += util_clkdiv_constr.xdc
M_DEPS += util_clkdiv_ip.tcl
M_VIVADO := vivado -mode batch -source

46
library/util_clkdiv/util_clkdiv.v
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@ -34,9 +34,9 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
// IP uses BUFR and BUFGMUX_CTRL primitive
// IP provides a glitch free output clock
// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
// clk_sel is 1. Provides a glitch free output clock
// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
// ***************************************************************************
// ***************************************************************************
@ -48,54 +48,56 @@ module util_clkdiv (
output clk_out
);
parameter C_SIM_DEVICE = "7SERIES";
parameter SIM_DEVICE = "7SERIES";
parameter SEL_0_DIV = "4";
parameter SEL_1_DIV = "2";
wire clk_div_2_s;
wire clk_div_4_s;
wire clk_div_sel_0_s;
wire clk_div_sel_1_s;
generate if (C_SIM_DEVICE == "7SERIES") begin
generate if (SIM_DEVICE == "7SERIES") begin
BUFR #(
.BUFR_DIVIDE("2"),
.BUFR_DIVIDE(SEL_0_DIV),
.SIM_DEVICE("7SERIES")
) clk_divide_2 (
) clk_divide_sel_0 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_2_s));
.O(clk_div_sel_0_s));
BUFR #(
.BUFR_DIVIDE("4"),
.BUFR_DIVIDE(SEL_1_DIV),
.SIM_DEVICE("7SERIES")
) clk_divide_4 (
) clk_divide_sel_1 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_4_s));
.O(clk_div_sel_1_s));
end else if (C_SIM_DEVICE == "ULTRASCALE") begin
end else if (SIM_DEVICE == "ULTRASCALE") begin
BUFGCE_DIV #(
.BUFGCE_DIVIDE("2")
) clk_divide_2 (
.BUFGCE_DIVIDE(SEL_0_DIV)
) clk_divide_sel_0 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_2_s));
.O(clk_div_sel_0_s));
BUFGCE_DIV #(
.BUFGCE_DIVIDE("4")
) clk_divide_4 (
.BUFGCE_DIVIDE(SEL_1_DIV)
) clk_divide_sel_1 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_4_s));
.O(clk_div_sel_1_s));
end endgenerate
BUFGMUX_CTRL i_div_clk_gbuf (
.I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
.I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
.S(clk_sel),
.O (clk_out));

2
library/util_clkdiv/util_clkdiv_constr.xdc
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@ -1,2 +1,2 @@
set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
set_clock_groups -group [get_clocks clk_div_sel_0_s] -group [get_clocks clk_div_sel_1_s] -logically_exclusive
set_false_path -to [get_pins i_div_clk_gbuf/S*]

10
library/util_clkdiv/util_clkdiv_ip.tcl
View File

@ -13,7 +13,13 @@ adi_ip_constraints util_clkdiv [list \
set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {BYPASS 0 1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {BYPASS 0 1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]