From 61be003017ef020d092a3b57eaf864d32cefbbb8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 15:24:14 +0200 Subject: [PATCH] axi_i2s/axi_spdif: Create clock and reset interface for DMA bus This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks. Signed-off-by: Lars-Peter Clausen --- library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 4 ++++ library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 3 +++ 2 files changed, 7 insertions(+) diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index b82b7dbd4..8d994fd72 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -28,6 +28,8 @@ adi_add_bus "DMA_REQ_RX" "axis" "master" \ {"DMA_REQ_RX_DRREADY" "TREADY"} \ {"DMA_REQ_RX_DRTYPE" "TUSER"} \ {"DMA_REQ_RX_DRLAST" "TLAST"} ] +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_RX_ACLK" "DMA_REQ_RX:DMA_ACK_RX" "DMA_REQ_RX_RSTN" adi_add_bus "DMA_ACK_TX" "axis" "slave" \ [list {"DMA_REQ_TX_DAVALID" "TVALID"} \ @@ -38,6 +40,8 @@ adi_add_bus "DMA_REQ_TX" "axis" "master" \ {"DMA_REQ_TX_DRREADY" "TREADY"} \ {"DMA_REQ_TX_DRTYPE" "TUSER"} \ {"DMA_REQ_TX_DRLAST" "TLAST"} ] +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_TX_ACLK" "DMA_REQ_TX:DMA_ACK_TX" "DMA_REQ_TX_RSTN" adi_set_bus_dependency "S_AXIS" "S_AXIS" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index 712af7492..793bd1123 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -32,6 +32,9 @@ adi_add_bus "DMA_REQ" "axis" "master" \ {"DMA_REQ_DRTYPE" "TUSER"} \ {"DMA_REQ_DRLAST" "TLAST"} ] +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN" + adi_set_bus_dependency "S_AXIS" "S_AXIS" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"