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fmcomms2/common: Add the util_tdd_sync module

main
Istvan Csomortani 2015-11-11 11:07:15 +02:00
parent fc0f4bc414
commit 6197a82c80
1 changed files with 11 additions and 3 deletions
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14
projects/fmcomms2/common/fmcomms2_bd.tcl
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@ -63,6 +63,8 @@ set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
# connections
ad_connect sys_200m_clk axi_ad9361/delay_clk
@ -137,9 +139,15 @@ ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect tdd_sync_o axi_ad9361/tdd_sync_o
ad_connect tdd_sync_i axi_ad9361/tdd_sync_i
ad_connect tdd_sync_t axi_ad9361/tdd_sync_t
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
ad_connect util_ad9361_tdd_sync/sync_en axi_ad9361/tdd_sync_en
ad_connect util_ad9361_tdd_sync/sync_type axi_ad9361/tdd_terminal_type
ad_connect tdd_sync_t axi_ad9361/tdd_terminal_type
ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
# interconnects