rfsom: updated to rfsom
Rejeesh Kutty
parent
4b571ded8f
commit
614dfcd93c
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@ -4,7 +4,6 @@
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set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
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set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
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set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
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set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
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set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
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@ -16,7 +15,26 @@ set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
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set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
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set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data]
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set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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# i2s
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set i2s_mclk [create_bd_port -dir O -type clk i2s_mclk]
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set i2s_bclk [create_bd_port -dir O i2s_bclk]
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set i2s_lrclk [create_bd_port -dir O i2s_lrclk]
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set i2s_sdata_out [create_bd_port -dir O i2s_sdata_out]
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set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in]
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# iic mux
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set iic_mux_scl_I [create_bd_port -dir I -from 1 -to 0 iic_mux_scl_I]
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set iic_mux_scl_O [create_bd_port -dir O -from 1 -to 0 iic_mux_scl_O]
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set iic_mux_scl_T [create_bd_port -dir O iic_mux_scl_T]
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set iic_mux_sda_I [create_bd_port -dir I -from 1 -to 0 iic_mux_sda_I]
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set iic_mux_sda_O [create_bd_port -dir O -from 1 -to 0 iic_mux_sda_O]
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set iic_mux_sda_T [create_bd_port -dir O iic_mux_sda_T ]
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set otg_vbusoc [create_bd_port -dir I otg_vbusoc]
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# spdif audio
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@ -37,12 +55,49 @@ set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 UART_0
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connect_bd_intf_net [get_bd_intf_pins sys_ps7/UART_0] [get_bd_intf_ports UART_0]
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set sys_rgmii [create_bd_cell -type ip -vlnv xilinx.com:ip:gmii_to_rgmii:3.0 sys_rgmii]
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set_property -dict [list CONFIG.SupportLevel {Include_Shared_Logic_in_Core}] $sys_rgmii
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connect_bd_intf_net [get_bd_intf_pins sys_ps7/MDIO_ETHERNET_1] [get_bd_intf_pins sys_rgmii/MDIO_GEM]
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connect_bd_intf_net [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] [get_bd_intf_pins sys_rgmii/GMII]
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 ETH1_MDIO
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 ETH1_RGMII
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create_bd_port -dir O -type clk ETH1_REFCLK
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create_bd_port -dir O -type clk ETH1_125MCLK
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create_bd_port -dir O -type clk ETH1_25MCLK
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create_bd_port -dir O -type clk ETH1_2M5CLK
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create_bd_port -dir O ETH1_LINK_STATUS
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create_bd_port -dir O ETH1_DUPLEX_STATUS
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create_bd_port -dir O -from 1 -to 0 ETH1_CLOCK_SPEED
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create_bd_port -dir O -from 1 -to 0 ETH1_SPEED_MODE
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create_bd_port -dir I -type intr ETH1_INTN
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connect_bd_intf_net [get_bd_intf_pins sys_rgmii/MDIO_PHY] [get_bd_intf_ports ETH1_MDIO]
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connect_bd_intf_net [get_bd_intf_pins sys_rgmii/RGMII] [get_bd_intf_ports ETH1_RGMII]
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connect_bd_net [get_bd_pins /sys_rgmii/ref_clk_out] [get_bd_ports ETH1_REFCLK]
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connect_bd_net [get_bd_pins /sys_rgmii/gmii_clk_125m_out] [get_bd_ports ETH1_125MCLK]
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connect_bd_net [get_bd_pins /sys_rgmii/gmii_clk_25m_out] [get_bd_ports ETH1_25MCLK]
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connect_bd_net [get_bd_pins /sys_rgmii/gmii_clk_2_5m_out] [get_bd_ports ETH1_2M5CLK]
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connect_bd_net [get_bd_pins /sys_rgmii/link_status] [get_bd_ports ETH1_LINK_STATUS]
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connect_bd_net [get_bd_pins /sys_rgmii/duplex_status] [get_bd_ports ETH1_DUPLEX_STATUS]
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connect_bd_net [get_bd_pins /sys_rgmii/clock_speed] [get_bd_ports ETH1_CLOCK_SPEED]
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connect_bd_net [get_bd_pins /sys_rgmii/speed_mode] [get_bd_ports ETH1_SPEED_MODE]
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connect_bd_net [get_bd_pins /sys_ps7/ENET1_EXT_INTIN] [get_bd_ports ETH1_INTN]
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
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set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
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set sys_i2c_mixer [create_bd_cell -type ip -vlnv analog.com:user:util_i2c_mixer:1.0 sys_i2c_mixer]
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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@ -53,6 +108,10 @@ set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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set sys_logic_inv [create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 sys_logic_inv]
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set_property -dict [list CONFIG.C_SIZE {1}] $sys_logic_inv
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set_property -dict [list CONFIG.C_OPERATION {not}] $sys_logic_inv
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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@ -78,6 +137,10 @@ set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_t
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set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
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set axi_i2s_adi [create_bd_cell -type ip -vlnv analog.com:user:axi_i2s_adi:1.0 axi_i2s_adi]
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set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_i2s_adi
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi
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# system reset/clock definitions
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set sys_100m_clk_source [get_bd_pins sys_ps7/FCLK_CLK0]
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@ -101,7 +164,6 @@ connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GP
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connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
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connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
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connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
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connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_main/iic]
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
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@ -117,6 +179,30 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESET
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
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connect_bd_net -net axi_iic_main_scl_i [get_bd_pins axi_iic_main/scl_i] [get_bd_pins sys_i2c_mixer/upstream_scl_O]
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connect_bd_net -net axi_iic_main_scl_o [get_bd_pins axi_iic_main/scl_o] [get_bd_pins sys_i2c_mixer/upstream_scl_I]
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connect_bd_net -net axi_iic_main_scl_t [get_bd_pins axi_iic_main/scl_t] [get_bd_pins sys_i2c_mixer/upstream_scl_T]
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connect_bd_net -net axi_iic_main_sda_i [get_bd_pins axi_iic_main/sda_i] [get_bd_pins sys_i2c_mixer/upstream_sda_O]
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connect_bd_net -net axi_iic_main_sda_o [get_bd_pins axi_iic_main/sda_o] [get_bd_pins sys_i2c_mixer/upstream_sda_I]
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connect_bd_net -net axi_iic_main_sda_t [get_bd_pins axi_iic_main/sda_t] [get_bd_pins sys_i2c_mixer/upstream_sda_T]
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connect_bd_net -net sys_i2c_mixer_downstream_scl_i [get_bd_ports iic_mux_scl_I] [get_bd_pins sys_i2c_mixer/downstream_scl_I]
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connect_bd_net -net sys_i2c_mixer_downstream_scl_o [get_bd_ports iic_mux_scl_O] [get_bd_pins sys_i2c_mixer/downstream_scl_O]
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connect_bd_net -net sys_i2c_mixer_downstream_scl_t [get_bd_ports iic_mux_scl_T] [get_bd_pins sys_i2c_mixer/downstream_scl_T]
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connect_bd_net -net sys_i2c_mixer_downstream_sda_i [get_bd_ports iic_mux_sda_I] [get_bd_pins sys_i2c_mixer/downstream_sda_I]
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connect_bd_net -net sys_i2c_mixer_downstream_sda_o [get_bd_ports iic_mux_sda_O] [get_bd_pins sys_i2c_mixer/downstream_sda_O]
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connect_bd_net -net sys_i2c_mixer_downstream_sda_t [get_bd_ports iic_mux_sda_T] [get_bd_pins sys_i2c_mixer/downstream_sda_T]
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connect_bd_net -net sys_logic_inv_o [get_bd_pins sys_logic_inv/Res] [get_bd_pins sys_ps7/USB0_VBUS_PWRFAULT]
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connect_bd_net -net sys_logic_inv_i [get_bd_pins sys_logic_inv/Op1] [get_bd_ports otg_vbusoc]
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set sys_rgmii_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rgmii_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rgmii_rstgen
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connect_bd_net -net sys_200m_clk [get_bd_pins sys_rgmii_rstgen/slowest_sync_clk]
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connect_bd_net -net sys_200m_clk [get_bd_pins sys_rgmii/clkin]
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connect_bd_net -net sys_aux_reset [get_bd_pins sys_rgmii_rstgen/ext_reset_in] [get_bd_pins sys_ps7/FCLK_RESET0_N]
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connect_bd_net [get_bd_pins sys_rgmii_rstgen/peripheral_reset] [get_bd_pins sys_rgmii/tx_reset] [get_bd_pins sys_rgmii/rx_reset]
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# hdmi
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@ -156,10 +242,10 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_24_hsync] [get_bd_ports hdmi_hsync]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_24_vsync] [get_bd_ports hdmi_vsync]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_24_data_e] [get_bd_ports hdmi_data_e]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_24_data] [get_bd_ports hdmi_data]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e]
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connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
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connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
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@ -187,10 +273,33 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_1
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connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
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connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
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# match up interconnects
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# i2s audio
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m05_axi [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_i2s_adi/s_axi]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/S_AXI_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_RX_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_TX_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA1_ACLK]
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connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA2_ACLK]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/S_AXI_ARESETN]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_RX_RSTN]
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_TX_RSTN]
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connect_bd_net -net sys_audio_clkgen_clk [get_bd_ports i2s_mclk]
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connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins axi_i2s_adi/DATA_CLK_I]
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connect_bd_net -net i2s_bclk_s [get_bd_ports i2s_bclk] [get_bd_pins axi_i2s_adi/BCLK_O]
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connect_bd_net -net i2s_lrclk_s [get_bd_ports i2s_lrclk] [get_bd_pins axi_i2s_adi/LRCLK_O]
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connect_bd_net -net i2s_sdata_out_s [get_bd_ports i2s_sdata_out] [get_bd_pins axi_i2s_adi/SDATA_O]
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connect_bd_net -net i2s_sdata_in_s [get_bd_ports i2s_sdata_in] [get_bd_pins axi_i2s_adi/SDATA_I]
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connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_tx [get_bd_intf_pins sys_ps7/DMA1_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_TX]
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connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA1_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_TX]
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connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_rx [get_bd_intf_pins sys_ps7/DMA2_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_RX]
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connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_rx [get_bd_intf_pins sys_ps7/DMA2_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_RX]
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connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
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connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
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@ -216,6 +325,7 @@ create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [g
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create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
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create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
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create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core
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create_bd_addr_seg -range 0x00010000 -offset 0x77600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_i2s_adi/S_AXI/reg0] SEG_data_i2s_adi
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create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
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Reference in New Issue