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util_clkdiv: Added division by 2 option

main
Adrian Costina 2016-11-24 16:01:37 +02:00
parent 91ee4394e4
commit 609b01f9e4
2 changed files with 30 additions and 14 deletions
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30
library/util_clkdiv/util_clkdiv.v
View File

@ -34,30 +34,44 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1 using
// BUFR and BUFGMUX primitives
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
module util_clkdiv ( module util_clkdiv (
clk, input clk,
clk_out input clk_sel,
output clk_out
); );
input clk; wire clk_div_2_s;
output clk_out; wire clk_div_4_s;
BUFR #(
.BUFR_DIVIDE("2"),
.SIM_DEVICE("7SERIES")
) clk_divide_2 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_2_s));
BUFR #( BUFR #(
.BUFR_DIVIDE("4"), .BUFR_DIVIDE("4"),
.SIM_DEVICE("7SERIES") .SIM_DEVICE("7SERIES")
) clk_divide ( ) clk_divide_4 (
.I(clk), .I(clk),
.CE(1), .CE(1),
.CLR(0), .CLR(0),
.O(clk_div_s)); .O(clk_div_4_s));
BUFG i_div_clk_gbuf ( BUFGMUX i_div_clk_gbuf (
.I (clk_div_s), .I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
.S(clk_sel),
.O (clk_out)); .O (clk_out));
endmodule // util_clkdiv endmodule // util_clkdiv

2
library/util_clkdiv/util_clkdiv_ip.tcl
View File

@ -7,4 +7,6 @@ adi_ip_files util_clkdiv [list \
adi_ip_properties_lite util_clkdiv adi_ip_properties_lite util_clkdiv
set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]