diff --git a/library/util_clkdiv/util_clkdiv.v b/library/util_clkdiv/util_clkdiv.v index a9b96a551..ee20fdb9f 100644 --- a/library/util_clkdiv/util_clkdiv.v +++ b/library/util_clkdiv/util_clkdiv.v @@ -34,30 +34,44 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** +// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1 using +// BUFR and BUFGMUX primitives // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps module util_clkdiv ( - clk, - clk_out + input clk, + input clk_sel, + output clk_out ); - input clk; - output clk_out; - + wire clk_div_2_s; + wire clk_div_4_s; + BUFR #( - .BUFR_DIVIDE("4"), + .BUFR_DIVIDE("2"), .SIM_DEVICE("7SERIES") - ) clk_divide ( + ) clk_divide_2 ( .I(clk), .CE(1), .CLR(0), - .O(clk_div_s)); - - BUFG i_div_clk_gbuf ( - .I (clk_div_s), + .O(clk_div_2_s)); + + BUFR #( + .BUFR_DIVIDE("4"), + .SIM_DEVICE("7SERIES") + ) clk_divide_4 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_4_s)); + + BUFGMUX i_div_clk_gbuf ( + .I0(clk_div_4_s), // 1-bit input: Clock input (S=0) + .I1(clk_div_2_s), // 1-bit input: Clock input (S=1) + .S(clk_sel), .O (clk_out)); endmodule // util_clkdiv diff --git a/library/util_clkdiv/util_clkdiv_ip.tcl b/library/util_clkdiv/util_clkdiv_ip.tcl index 66286de2a..701ca5c96 100644 --- a/library/util_clkdiv/util_clkdiv_ip.tcl +++ b/library/util_clkdiv/util_clkdiv_ip.tcl @@ -1,10 +1,12 @@ source ../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip.tcl - + adi_ip_create util_clkdiv adi_ip_files util_clkdiv [list \ "util_clkdiv.v" ] - + adi_ip_properties_lite util_clkdiv - + +set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] + ipx::save_core [ipx::current_core]