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axi_dacfifo: Move the axi_dac_fifo_bypass module to util_dac_fifo_bypass

main
Istvan Csomortani 2017-04-21 13:23:03 +03:00
parent 2379514ae6
commit 5fe7a1b100
4 changed files with 4 additions and 4 deletions
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2
library/xilinx/axi_dacfifo/axi_dacfifo_bypass.v → library/common/util_dacfifo_bypass.v
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@ -39,7 +39,7 @@
`timescale 1ns/100ps
module axi_dacfifo_bypass #(
module util_dacfifo_bypass #(
parameter DAC_DATA_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64) (

2
library/xilinx/axi_dacfifo/axi_dacfifo.v
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@ -250,7 +250,7 @@ module axi_dacfifo #(
generate
if (FIFO_BYPASS) begin
axi_dacfifo_bypass #(
util_dacfifo_bypass #(
.DAC_DATA_WIDTH (DAC_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH)
) i_dacfifo_bypass (

2
library/xilinx/axi_dacfifo/axi_dacfifo_hw.tcl
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@ -7,10 +7,10 @@ ad_ip_create axi_dacfifo {AXI DAC FIFO Interface}
ad_ip_files axi_dacfifo [list\
$ad_hdl_dir/library/altera/common/ad_mem_asym.v \
$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
$ad_hdl_dir/library/common/util_dacfifo_bypass.v \
axi_dacfifo_dac.v \
axi_dacfifo_wr.v \
axi_dacfifo_rd.v \
axi_dacfifo_bypass.v \
axi_dacfifo.v \
axi_dacfifo_constr.sdc]

2
library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl
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@ -8,11 +8,11 @@ adi_ip_create axi_dacfifo
adi_ip_files axi_dacfifo [list \
"$ad_hdl_dir/library/common/ad_mem_asym.v" \
"$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \
"$ad_hdl_dir/library/common/util_dacfifo_bypass.v" \
"axi_dacfifo_constr.xdc" \
"axi_dacfifo_dac.v" \
"axi_dacfifo_wr.v" \
"axi_dacfifo_rd.v" \
"axi_dacfifo_bypass.v" \
"axi_dacfifo.v"]
adi_ip_properties_lite axi_dacfifo