m2k: standalone: Rework PS7 clocking

At the moment the PS7 is using three PLLs to generate its clocking tree.
One for the DDR, one for the ARM and one for the IO. This allows to run all
components at their respective maximum clock and extract maximum
performance from all components.

With some slight modifications it is possible to trade maximum performance
for a reduction in power consumption by using the same PLL for all three
sets of components and disabling the other two PLLs.

The CPU is now running at 500MHz rather than 666MHz and the DDR memory at
500MHz rather than 533MHz. This reduces power consumption by ~125mW.

This is OK since neither of them is a bottleneck for overall system
performance.

In addition software will downclock the CPU to 250MHz when full performance
is not required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

projects/m2k/standalone/system_bd.tcl

@@ -73,6 +73,42 @@ set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
 set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
 
+# Clock the whole system of the DDR PLL, disable ARM and IO PLL
+# * PLL: 1000 MHz
+# * DDR: 500 MHz (2.0Gb/s),
+# * CPU: 500 MHz (downclocked to 250 MHz when idle)
+set_property -dict [list \
+	CONFIG.PCW_OVERRIDE_BASIC_CLOCK {1} \
+	CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
+	CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \
+	CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {20} \
+	CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {16} \
+	CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {6} \
+	CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {40} \
+	CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {40} \
+	CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6} \
+	CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6} \
+	CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {5} \
+	CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2} \
+	CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {6} \
+	CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {3} \
+	CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
+	CONFIG.PCW_ARMPLL_CTRL_FBDIV {30} \
+	CONFIG.PCW_DDRPLL_CTRL_FBDIV {30} \
+	CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_UART_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {DDR PLL} \
+	CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500} \
+	CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {500}
+] [get_bd_cells sys_ps7]
+
 # DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
 
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
@@ -85,6 +121,7 @@ set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
 set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
+set_property -dict [list CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500.0}] $sys_ps7
 
 set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]