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fmcjesdadc1: zc706 version

main
Rejeesh Kutty 2014-08-25 14:28:57 -04:00
parent cb29b83b05
commit 5f21f54463
6 changed files with 387 additions and 378 deletions
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2
library/axi_ad9250/axi_ad9250.v
View File

@ -266,7 +266,7 @@ module axi_ad9250 (
.delay_wdata (),
.delay_rdata (5'd0),
.delay_ack_t (1'b0),
.delay_locked (1'b0),
.delay_locked (1'b1),
.drp_clk (1'd0),
.drp_rst (),
.drp_sel (),

419
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
View File

@ -1,17 +1,8 @@
# ad9625
if {$sys_zynq == 1} {
set spi_csn_1_o [create_bd_port -dir O spi_csn_1_o]
set spi_csn_0_o [create_bd_port -dir O spi_csn_0_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
} else {
set spi_csn_o [create_bd_port -dir O -from 1 -to 0 spi_csn_o]
set spi_csn_i [create_bd_port -dir I -from 1 -to 0 spi_csn_i]
}
# ad9250
set spi_csn_o [create_bd_port -dir O spi_csn_o]
set spi_csn_i [create_bd_port -dir I spi_csn_i]
set spi_clk_i [create_bd_port -dir I spi_clk_i]
set spi_clk_o [create_bd_port -dir O spi_clk_o]
set spi_sdo_i [create_bd_port -dir I spi_sdo_i]
@ -21,106 +12,130 @@ set spi_sdi_i [create_bd_port -dir I spi_sdi_i]
set rx_ref_clk [create_bd_port -dir I rx_ref_clk]
set rx_sync [create_bd_port -dir O rx_sync]
set rx_sysref [create_bd_port -dir O rx_sysref]
set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n]
set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p]
set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n]
if {$sys_zynq == 0} {
set rx_gt_data [create_bd_port -dir O -from 127 -to 0 rx_gt_data]
set rx_gt_data_0 [create_bd_port -dir I -from 63 -to 0 rx_gt_data_0]
set rx_gt_data_1 [create_bd_port -dir I -from 63 -to 0 rx_gt_data_1]
set gpio_ad9625_i [create_bd_port -dir I -from 1 -to 0 gpio_ad9625_i]
set gpio_ad9625_o [create_bd_port -dir O -from 1 -to 0 gpio_ad9625_o]
set gpio_ad9625_t [create_bd_port -dir O -from 1 -to 0 gpio_ad9625_t]
}
set adc_clk [create_bd_port -dir O adc_clk]
set adc_0_enable_a [create_bd_port -dir O adc_0_enable_a]
set adc_0_valid_a [create_bd_port -dir O adc_0_valid_a]
set adc_0_data_a [create_bd_port -dir O -from 31 -to 0 adc_0_data_a]
set adc_0_enable_b [create_bd_port -dir O adc_0_enable_b]
set adc_0_valid_b [create_bd_port -dir O adc_0_valid_b]
set adc_0_data_b [create_bd_port -dir O -from 31 -to 0 adc_0_data_b]
set adc_1_enable_a [create_bd_port -dir O adc_1_enable_a]
set adc_1_valid_a [create_bd_port -dir O adc_1_valid_a]
set adc_1_data_a [create_bd_port -dir O -from 31 -to 0 adc_1_data_a]
set adc_1_enable_b [create_bd_port -dir O adc_1_enable_b]
set adc_1_valid_b [create_bd_port -dir O adc_1_valid_b]
set adc_1_data_b [create_bd_port -dir O -from 31 -to 0 adc_1_data_b]
set dma_0_wr [create_bd_port -dir I dma_0_wr]
set dma_0_sync [create_bd_port -dir I dma_0_sync]
set dma_0_data [create_bd_port -dir I -from 63 -to 0 dma_0_data]
set dma_1_wr [create_bd_port -dir I dma_1_wr]
set dma_1_sync [create_bd_port -dir I dma_1_sync]
set dma_1_data [create_bd_port -dir I -from 63 -to 0 dma_1_data]
# adc peripherals
set axi_ad9625_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_core]
set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core]
set axi_ad9250_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_1_core]
set axi_ad9625_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9625_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_jesd
set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_jesd
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9250_jesd]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd
set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9250_jesd
set axi_ad9625_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_gt
set axi_ad9250_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9250_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {10}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9250_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9250_gt
set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9625_dma
set axi_ad9250_0_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_0_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_0_dma
set axi_ad9250_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
if {$sys_zynq == 1} {
set axi_ad9625_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9625_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9625_gt_interconnect
set axi_ad9250_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9250_gt_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9250_gt_interconnect
set axi_ad9625_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9625_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9625_dma_interconnect
set axi_ad9250_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9250_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9250_dma_interconnect
set_property -dict [list CONFIG.NUM_SI {2}] $axi_ad9250_dma_interconnect
}
# spi
if {$sys_zynq == 0} {
set axi_ad9625_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_ad9625_gpio]
set_property -dict [list CONFIG.C_IS_DUAL {0}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_GPIO_WIDTH {2}] $axi_ad9625_gpio
set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_ad9625_gpio
set axi_ad9625_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_ad9625_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $axi_ad9625_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9625_spi
set axi_ad9250_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_ad9250_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_ad9250_spi
set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $axi_ad9250_spi
set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_ad9250_spi
}
# additions to default configuration
if {$sys_zynq == 1} {
set_property -dict [list CONFIG.NUM_MI {11}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property LEFT 16 [get_bd_ports GPIO_I]
set_property LEFT 16 [get_bd_ports GPIO_O]
set_property LEFT 16 [get_bd_ports GPIO_T]
} else {
set_property -dict [list CONFIG.NUM_MI {13}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_SI {10}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect
set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect
set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc
delete_bd_objs [get_bd_nets sys_concat_intc_din_2]
delete_bd_objs [get_bd_ports unc_int2]
delete_bd_objs [get_bd_nets sys_concat_intc_din_3]
delete_bd_objs [get_bd_ports unc_int3]
}
# connections (spi and gpio)
if {$sys_zynq == 1 } {
connect_bd_net -net spi_csn_1_o [get_bd_ports spi_csn_1_o] [get_bd_pins sys_ps7/SPI0_SS1_O]
connect_bd_net -net spi_csn_0_o [get_bd_ports spi_csn_0_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
@ -130,119 +145,146 @@ if {$sys_zynq == 1 } {
} else {
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9625_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9625_spi/ss_o]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9625_spi/sck_i]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9625_spi/sck_o]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9625_spi/io0_i]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9625_spi/io0_o]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9625_spi/io1_i]
connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9250_spi/ss_i]
connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9250_spi/ss_o]
connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9250_spi/sck_i]
connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9250_spi/sck_o]
connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9250_spi/io0_i]
connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9250_spi/io0_o]
connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9250_spi/io1_i]
connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins axi_ad9625_gpio/gpio_io_i]
connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o]
connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t]
connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6]
connect_bd_net -net axi_ad9250_spi_irq [get_bd_pins axi_ad9250_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5]
}
# connections (gt)
connect_bd_net -net axi_ad9625_gt_ref_clk_c [get_bd_pins axi_ad9625_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_ad9625_gt_rx_data_p [get_bd_pins axi_ad9625_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_ad9625_gt_rx_data_n [get_bd_pins axi_ad9625_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_ad9625_gt_rx_sync [get_bd_pins axi_ad9625_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_ad9625_gt_rx_sysref [get_bd_pins axi_ad9625_gt/rx_sysref] [get_bd_ports rx_sysref]
connect_bd_net -net axi_ad9250_gt_ref_clk_c [get_bd_pins axi_ad9250_gt/ref_clk_c] [get_bd_ports rx_ref_clk]
connect_bd_net -net axi_ad9250_gt_rx_data_p [get_bd_pins axi_ad9250_gt/rx_data_p] [get_bd_ports rx_data_p]
connect_bd_net -net axi_ad9250_gt_rx_data_n [get_bd_pins axi_ad9250_gt/rx_data_n] [get_bd_ports rx_data_n]
connect_bd_net -net axi_ad9250_gt_rx_sync [get_bd_pins axi_ad9250_gt/rx_sync] [get_bd_ports rx_sync]
connect_bd_net -net axi_ad9250_gt_rx_sysref [get_bd_pins axi_ad9250_gt/rx_sysref] [get_bd_ports rx_sysref]
# connections (adc)
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_gt/rx_clk_g]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_gt/rx_clk]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_core/rx_clk]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins axi_ad9625_jesd/rx_core_clk]
connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_gt/rx_rst]
connect_bd_net -net axi_ad9625_gt_rx_rst [get_bd_pins axi_ad9625_jesd/rx_reset]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_gt/rx_clk_g]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_gt/rx_clk]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_0_core/rx_clk]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_1_core/rx_clk]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins axi_ad9250_jesd/rx_core_clk]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_ports adc_clk]
connect_bd_net -net axi_ad9250_gt_rx_rst [get_bd_pins axi_ad9250_gt/rx_rst]
connect_bd_net -net axi_ad9250_gt_rx_rst [get_bd_pins axi_ad9250_jesd/rx_reset]
connect_bd_net -net axi_ad9625_gt_rx_sysref [get_bd_pins axi_ad9625_jesd/rx_sysref]
connect_bd_net -net axi_ad9625_gt_rx_gt_charisk [get_bd_pins axi_ad9625_gt/rx_gt_charisk] [get_bd_pins axi_ad9625_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9625_gt_rx_gt_disperr [get_bd_pins axi_ad9625_gt/rx_gt_disperr] [get_bd_pins axi_ad9625_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9625_gt_rx_gt_notintable [get_bd_pins axi_ad9625_gt/rx_gt_notintable] [get_bd_pins axi_ad9625_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9625_gt_rx_gt_data [get_bd_pins axi_ad9625_gt/rx_gt_data] [get_bd_pins axi_ad9625_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9625_gt_rx_rst_done [get_bd_pins axi_ad9625_gt/rx_rst_done] [get_bd_pins axi_ad9625_jesd/rx_reset_done]
connect_bd_net -net axi_ad9625_gt_rx_ip_comma_align [get_bd_pins axi_ad9625_gt/rx_ip_comma_align] [get_bd_pins axi_ad9625_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9625_gt_rx_ip_sync [get_bd_pins axi_ad9625_gt/rx_ip_sync] [get_bd_pins axi_ad9625_jesd/rx_sync]
connect_bd_net -net axi_ad9625_gt_rx_ip_sof [get_bd_pins axi_ad9625_gt/rx_ip_sof] [get_bd_pins axi_ad9625_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9625_gt_rx_ip_data [get_bd_pins axi_ad9625_gt/rx_ip_data] [get_bd_pins axi_ad9625_jesd/rx_tdata]
connect_bd_net -net axi_ad9625_gt_rx_data [get_bd_pins axi_ad9625_gt/rx_data] [get_bd_pins axi_ad9625_core/rx_data]
connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_valid] [get_bd_pins axi_ad9625_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9625_dma_irq [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9250_gt_rx_sysref [get_bd_pins axi_ad9250_jesd/rx_sysref]
connect_bd_net -net axi_ad9250_gt_rx_gt_charisk [get_bd_pins axi_ad9250_gt/rx_gt_charisk] [get_bd_pins axi_ad9250_jesd/gt_rxcharisk_in]
connect_bd_net -net axi_ad9250_gt_rx_gt_disperr [get_bd_pins axi_ad9250_gt/rx_gt_disperr] [get_bd_pins axi_ad9250_jesd/gt_rxdisperr_in]
connect_bd_net -net axi_ad9250_gt_rx_gt_notintable [get_bd_pins axi_ad9250_gt/rx_gt_notintable] [get_bd_pins axi_ad9250_jesd/gt_rxnotintable_in]
connect_bd_net -net axi_ad9250_gt_rx_gt_data [get_bd_pins axi_ad9250_gt/rx_gt_data] [get_bd_pins axi_ad9250_jesd/gt_rxdata_in]
connect_bd_net -net axi_ad9250_gt_rx_rst_done [get_bd_pins axi_ad9250_gt/rx_rst_done] [get_bd_pins axi_ad9250_jesd/rx_reset_done]
connect_bd_net -net axi_ad9250_gt_rx_ip_comma_align [get_bd_pins axi_ad9250_gt/rx_ip_comma_align] [get_bd_pins axi_ad9250_jesd/rxencommaalign_out]
connect_bd_net -net axi_ad9250_gt_rx_ip_sync [get_bd_pins axi_ad9250_gt/rx_ip_sync] [get_bd_pins axi_ad9250_jesd/rx_sync]
connect_bd_net -net axi_ad9250_gt_rx_ip_sof [get_bd_pins axi_ad9250_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame]
connect_bd_net -net axi_ad9250_gt_rx_ip_data [get_bd_pins axi_ad9250_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata]
connect_bd_net -net axi_ad9250_gt_rx_data [get_bd_pins axi_ad9250_gt/rx_data] [get_bd_ports rx_gt_data]
connect_bd_net -net axi_ad9250_0_gt_rx_data [get_bd_pins axi_ad9250_0_core/rx_data] [get_bd_ports rx_gt_data_0]
connect_bd_net -net axi_ad9250_1_gt_rx_data [get_bd_pins axi_ad9250_1_core/rx_data] [get_bd_ports rx_gt_data_1]
connect_bd_net -net axi_ad9250_0_adc_clk [get_bd_pins axi_ad9250_0_core/adc_clk] [get_bd_pins axi_ad9250_0_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9250_1_adc_clk [get_bd_pins axi_ad9250_1_core/adc_clk] [get_bd_pins axi_ad9250_1_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9250_0_adc_enable_a [get_bd_pins axi_ad9250_0_core/adc_enable_a] [get_bd_ports adc_0_enable_a]
connect_bd_net -net axi_ad9250_0_adc_valid_a [get_bd_pins axi_ad9250_0_core/adc_valid_a] [get_bd_ports adc_0_valid_a]
connect_bd_net -net axi_ad9250_0_adc_data_a [get_bd_pins axi_ad9250_0_core/adc_data_a] [get_bd_ports adc_0_data_a]
connect_bd_net -net axi_ad9250_0_adc_enable_b [get_bd_pins axi_ad9250_0_core/adc_enable_b] [get_bd_ports adc_0_enable_b]
connect_bd_net -net axi_ad9250_0_adc_valid_b [get_bd_pins axi_ad9250_0_core/adc_valid_b] [get_bd_ports adc_0_valid_b]
connect_bd_net -net axi_ad9250_0_adc_data_b [get_bd_pins axi_ad9250_0_core/adc_data_b] [get_bd_ports adc_0_data_b]
connect_bd_net -net axi_ad9250_1_adc_enable_a [get_bd_pins axi_ad9250_1_core/adc_enable_a] [get_bd_ports adc_1_enable_a]
connect_bd_net -net axi_ad9250_1_adc_valid_a [get_bd_pins axi_ad9250_1_core/adc_valid_a] [get_bd_ports adc_1_valid_a]
connect_bd_net -net axi_ad9250_1_adc_data_a [get_bd_pins axi_ad9250_1_core/adc_data_a] [get_bd_ports adc_1_data_a]
connect_bd_net -net axi_ad9250_1_adc_enable_b [get_bd_pins axi_ad9250_1_core/adc_enable_b] [get_bd_ports adc_1_enable_b]
connect_bd_net -net axi_ad9250_1_adc_valid_b [get_bd_pins axi_ad9250_1_core/adc_valid_b] [get_bd_ports adc_1_valid_b]
connect_bd_net -net axi_ad9250_1_adc_data_b [get_bd_pins axi_ad9250_1_core/adc_data_b] [get_bd_ports adc_1_data_b]
connect_bd_net -net axi_ad9250_0_dma_wr [get_bd_pins axi_ad9250_0_dma/fifo_wr_en] [get_bd_ports dma_0_wr]
connect_bd_net -net axi_ad9250_0_dma_sync [get_bd_pins axi_ad9250_0_dma/fifo_wr_sync] [get_bd_ports dma_0_sync]
connect_bd_net -net axi_ad9250_0_dma_data [get_bd_pins axi_ad9250_0_dma/fifo_wr_din] [get_bd_ports dma_0_data]
connect_bd_net -net axi_ad9250_1_dma_wr [get_bd_pins axi_ad9250_1_dma/fifo_wr_en] [get_bd_ports dma_1_wr]
connect_bd_net -net axi_ad9250_1_dma_sync [get_bd_pins axi_ad9250_1_dma/fifo_wr_sync] [get_bd_ports dma_1_sync]
connect_bd_net -net axi_ad9250_1_dma_data [get_bd_pins axi_ad9250_1_dma/fifo_wr_din] [get_bd_ports dma_1_data]
connect_bd_net -net axi_ad9250_0_adc_dovf [get_bd_pins axi_ad9250_0_core/adc_dovf] [get_bd_pins axi_ad9250_0_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9250_1_adc_dovf [get_bd_pins axi_ad9250_1_core/adc_dovf] [get_bd_pins axi_ad9250_1_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In2]
connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In3]
# interconnect (cpu)
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9625_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9625_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9625_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9625_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9250_0_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9250_0_core/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9250_jesd/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9250_gt/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9250_1_dma/s_axi]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9250_1_core/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_0_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_1_core/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_jesd/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_0_dma/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_1_dma/s_axi_aclk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_0_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_1_core/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_jesd/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_0_dma/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_1_dma/s_axi_aresetn]
if {$sys_zynq == 0} {
connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9625_spi/axi_lite]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9625_gpio/s_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gpio/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_spi/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_spi/s_axi_aresetn]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gpio/s_axi_aresetn]
connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_ad9250_spi/axi_lite]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_spi/s_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_spi/ext_spi_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_spi/s_axi_aresetn]
}
# interconnect (gt es)
if {$sys_zynq == 1} {
connect_bd_intf_net -intf_net axi_ad9625_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9625_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9625_gt/m_axi]
connect_bd_intf_net -intf_net axi_ad9625_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9625_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_intf_net -intf_net axi_ad9250_gt_interconnect_s00_axi [get_bd_intf_pins axi_ad9250_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9250_gt/m_axi]
connect_bd_intf_net -intf_net axi_ad9250_gt_interconnect_m00_axi [get_bd_intf_pins axi_ad9250_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt_interconnect/ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt_interconnect/M00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt_interconnect/S00_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt_interconnect/ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source
} else {
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9625_gt/m_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_ad9250_gt/m_axi]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source
}
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9625_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9625_gt/m_axi_aresetn]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt/m_axi_aclk]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9250_gt/drp_clk]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9250_gt/m_axi_aresetn]
# interconnect (dma)
@ -254,63 +296,82 @@ if {$sys_zynq == 1} {
connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
connect_bd_intf_net -intf_net axi_ad9625_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9625_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9625_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9625_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2]
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9250_0_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_ad9250_dma_interconnect_s01_axi [get_bd_intf_pins axi_ad9250_dma_interconnect/S01_AXI] [get_bd_intf_pins axi_ad9250_1_dma/m_dest_axi]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_dma_interconnect/S01_ACLK] $sys_fmc_dma_clk_source
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aclk]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma_interconnect/S01_ARESETN] $sys_fmc_dma_resetn_source
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aresetn]
} else {
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9625_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9250_0_dma/m_dest_axi]
connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9250_1_dma/m_dest_axi]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9625_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aclk]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9625_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9250_0_dma/m_dest_axi_aresetn]
connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9250_1_dma/m_dest_axi_aresetn]
}
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {7}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {32}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE4_WIDTH {32}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE5_WIDTH {32}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE6_WIDTH {32}] $ila_jesd_rx_mon
connect_bd_net -net axi_ad9625_gt_rx_mon_data [get_bd_pins axi_ad9625_gt/rx_mon_data]
connect_bd_net -net axi_ad9625_gt_rx_mon_trigger [get_bd_pins axi_ad9625_gt/rx_mon_trigger]
connect_bd_net -net axi_ad9625_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_ad9625_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_ad9625_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_ad9625_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3]
connect_bd_net -net axi_ad9250_gt_rx_mon_data [get_bd_pins axi_ad9250_gt/rx_mon_data]
connect_bd_net -net axi_ad9250_gt_rx_mon_trigger [get_bd_pins axi_ad9250_gt/rx_mon_trigger]
connect_bd_net -net axi_ad9250_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK]
connect_bd_net -net axi_ad9250_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
connect_bd_net -net axi_ad9250_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
connect_bd_net -net axi_ad9250_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
connect_bd_net -net axi_ad9250_0_adc_data_a [get_bd_pins ila_jesd_rx_mon/PROBE3]
connect_bd_net -net axi_ad9250_0_adc_data_b [get_bd_pins ila_jesd_rx_mon/PROBE4]
connect_bd_net -net axi_ad9250_1_adc_data_a [get_bd_pins ila_jesd_rx_mon/PROBE5]
connect_bd_net -net axi_ad9250_1_adc_data_b [get_bd_pins ila_jesd_rx_mon/PROBE6]
# address map
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_core/s_axi/axi_lite] SEG_data_ad9625_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_gt/s_axi/axi_lite] SEG_data_ad9625_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_jesd/s_axi/Reg] SEG_data_ad9625_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_dma/s_axi/axi_lite] SEG_data_ad9625_dma
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_0_core/s_axi/axi_lite] SEG_data_ad9250_0_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_1_core/s_axi/axi_lite] SEG_data_ad9250_1_core
create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_gt/s_axi/axi_lite] SEG_data_ad9250_gt
create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_jesd/s_axi/Reg] SEG_data_ad9250_jesd
create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_0_dma/s_axi/axi_lite] SEG_data_ad9250_0_dma
create_bd_addr_seg -range 0x00010000 -offset 0x7c430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_1_dma/s_axi/axi_lite] SEG_data_ad9250_1_dma
if {$sys_zynq == 0} {
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9625_spi/axi_lite/Reg] SEG_data_ad9625_spi
create_bd_addr_seg -range 0x00010000 -offset 0x40030000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ad9625_gpio/s_axi/Reg] SEG_data_gpio_3
create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9250_spi/axi_lite/Reg] SEG_data_ad9250_spi
}
if {$sys_zynq == 1} {
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_0_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9250_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
} else {
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9625_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9250_0_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9250_1_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9250_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl
}

51
projects/fmcjesdadc1/zc706/system_bd.tcl
View File

@ -1,54 +1,5 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
source ../common/ad9625_fmc_bd.tcl
source ../common/fmcjesdadc1_bd.tcl
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
p_plddr3_fifo [current_bd_instance .] plddr3_fifo 256
set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3]
set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3]
connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk]
delete_bd_objs [get_bd_nets axi_ad9625_adc_clk]
delete_bd_objs [get_bd_nets axi_ad9625_adc_enable]
delete_bd_objs [get_bd_nets axi_ad9625_adc_data]
delete_bd_objs [get_bd_nets axi_ad9625_adc_dovf]
delete_bd_objs [get_bd_nets axi_ad9625_adc_valid]
connect_bd_net -net [get_bd_nets axi_ad9625_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_ad9625_gt/rx_rst]
connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_ps7/FCLK_RESET2_N]
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req]
connect_bd_net -net axi_ad9625_adc_clk [get_bd_pins axi_ad9625_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins plddr3_fifo/adc_wr]
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins axi_ad9625_core/adc_data] [get_bd_pins plddr3_fifo/adc_wdata]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf]
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
connect_bd_net -net axi_ad9625_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9625_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9625_adc_valid [get_bd_pins axi_ad9625_core/adc_valid] [get_bd_pins axi_ad9625_dma/fifo_wr_sync]
connect_bd_net -net axi_ad9625_adc_data [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins ila_dma_mon/clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0]
connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins ila_dma_mon/probe1]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2]
connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status]
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr

48
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -1,5 +1,5 @@
# ad9625
# ad9250
set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N
@ -11,45 +11,25 @@ set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]]
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[4]] ; ## B12 FMC_HPC_DP7_M2C_P
set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[4]] ; ## B13 FMC_HPC_DP7_M2C_N
set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[5]] ; ## A14 FMC_HPC_DP4_M2C_P
set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[5]] ; ## A15 FMC_HPC_DP4_M2C_N
set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[6]] ; ## B16 FMC_HPC_DP6_M2C_P
set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[6]] ; ## B17 FMC_HPC_DP6_M2C_N
set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[7]] ; ## A18 FMC_HPC_DP5_M2C_P
set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[7]] ; ## A19 FMC_HPC_DP5_M2C_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports rx_sync] ; ## G36 FMC_HPC_LA33_P
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports rx_sysref] ; ## G37 FMC_HPC_LA33_N
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports spi_adc_csn] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports spi_adc_clk] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports spi_adc_sdio] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports spi_clk_csn] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports spi_clk_clk] ; ## G06 FMC_HPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports spi_clk_sdio] ; ## G07 FMC_HPC_LA00_CC_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_irq] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## G34 FMC_HPC_LA31_N
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_HPC_LA32_P
# clocks
create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_nets i_system_wrapper/system_i/axi_ad9625_gt_rx_clk]
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 8.80 [get_nets i_system_wrapper/system_i/axi_ad9250_gt_rx_clk]
create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2]
create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk]
create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0]
set_clock_groups -asynchronous -group {rx_div_clk}
set_clock_groups -asynchronous -group {fmc_dma_clk}
set_clock_groups -asynchronous -group {pl_ddr_clk}
set_clock_groups -asynchronous -group {pl_dma_clk}
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9625_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE]
set_false_path -through [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE]

9
projects/fmcjesdadc1/zc706/system_project.tcl
View File

@ -4,15 +4,14 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
adi_project_create ad9625_fmc_zc706
adi_project_files ad9625_fmc_zc706 [list \
adi_project_create fmcjesdadc1_zc706
adi_project_files fmcjesdadc1_zc706 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"../common/ad9625_fmc_spi.v" \
"../common/fmcjesdadc1_spi.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run ad9625_fmc_zc706
adi_project_run fmcjesdadc1_zc706

236
projects/fmcjesdadc1/zc706/system_top.v
View File

@ -41,22 +41,6 @@
module system_top (
DDR3_addr,
DDR3_ba,
DDR3_cas_n,
DDR3_ck_n,
DDR3_ck_p,
DDR3_cke,
DDR3_cs_n,
DDR3_dm,
DDR3_dq,
DDR3_dqs_n,
DDR3_dqs_p,
DDR3_odt,
DDR3_ras_n,
DDR3_reset_n,
DDR3_we_n,
DDR_addr,
DDR_ba,
DDR_cas_n,
@ -82,9 +66,6 @@ module system_top (
gpio_bd,
sys_clk_p,
sys_clk_n,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
@ -98,38 +79,14 @@ module system_top (
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_sysref,
rx_sync,
rx_data_p,
rx_data_n,
adc_irq,
adc_fd,
spi_adc_csn,
spi_adc_clk,
spi_adc_sdio,
spi_clk_csn,
spi_clk_clk,
spi_clk_sdio);
output [13:0] DDR3_addr;
output [ 2:0] DDR3_ba;
output DDR3_cas_n;
output [ 0:0] DDR3_ck_n;
output [ 0:0] DDR3_ck_p;
output [ 0:0] DDR3_cke;
output [ 0:0] DDR3_cs_n;
output [ 7:0] DDR3_dm;
inout [63:0] DDR3_dq;
inout [ 7:0] DDR3_dqs_n;
inout [ 7:0] DDR3_dqs_p;
output [ 0:0] DDR3_odt;
output DDR3_ras_n;
output DDR3_reset_n;
output DDR3_we_n;
spi_csn,
spi_clk,
spi_sdio);
inout [14:0] DDR_addr;
inout [ 2:0] DDR_ba;
@ -156,9 +113,6 @@ module system_top (
inout [14:0] gpio_bd;
input sys_clk_p;
input sys_clk_n;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
@ -172,34 +126,108 @@ module system_top (
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
output rx_sysref;
output rx_sync;
input [ 3:0] rx_data_p;
input [ 3:0] rx_data_n;
inout adc_irq;
inout adc_fd;
output spi_csn;
output spi_clk;
inout spi_sdio;
output spi_adc_csn;
output spi_adc_clk;
inout spi_adc_sdio;
output spi_clk_csn;
output spi_clk_clk;
inout spi_clk_sdio;
// internal registers
reg dma_0_wr = 'd0;
reg [63:0] dma_0_data = 'd0;
reg dma_1_wr = 'd0;
reg [63:0] dma_1_data = 'd0;
// internal signals
wire [16:0] gpio_i;
wire [16:0] gpio_o;
wire [16:0] gpio_t;
wire [14:0] gpio_i;
wire [14:0] gpio_o;
wire [14:0] gpio_t;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire spi_clk;
wire spi_miso;
wire spi_mosi;
wire adc_clk;
wire [127:0] rx_gt_data;
wire adc_0_enable_a;
wire [31:0] adc_0_data_a;
wire adc_0_enable_b;
wire [31:0] adc_0_data_b;
wire adc_1_enable_a;
wire [31:0] adc_1_data_a;
wire adc_1_enable_b;
wire [31:0] adc_1_data_b;
// pack & unpack here
always @(posedge adc_clk) begin
case ({adc_0_enable_b, adc_0_enable_a})
2'b11: begin
dma_0_wr <= 1'b1;
dma_0_data[63:48] <= adc_0_data_b[31:16];
dma_0_data[47:32] <= adc_0_data_a[31:16];
dma_0_data[31:16] <= adc_0_data_b[15: 0];
dma_0_data[15: 0] <= adc_0_data_a[15: 0];
end
2'b10: begin
dma_0_wr <= ~dma_0_wr;
dma_0_data[63:48] <= adc_0_data_b[31:16];
dma_0_data[47:32] <= adc_0_data_b[15: 0];
dma_0_data[31:16] <= dma_0_data[63:48];
dma_0_data[15: 0] <= dma_0_data[47:32];
end
2'b01: begin
dma_0_wr <= ~dma_0_wr;
dma_0_data[63:48] <= adc_0_data_a[31:16];
dma_0_data[47:32] <= adc_0_data_a[15: 0];
dma_0_data[31:16] <= dma_0_data[63:48];
dma_0_data[15: 0] <= dma_0_data[47:32];
end
default: begin
dma_0_wr <= 1'b0;
dma_0_data[63:48] <= 16'd0;
dma_0_data[47:32] <= 16'd0;
dma_0_data[31:16] <= 16'd0;
dma_0_data[15: 0] <= 16'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_1_enable_b, adc_1_enable_a})
2'b11: begin
dma_1_wr <= 1'b1;
dma_1_data[63:48] <= adc_1_data_b[31:16];
dma_1_data[47:32] <= adc_1_data_a[31:16];
dma_1_data[31:16] <= adc_1_data_b[15: 0];
dma_1_data[15: 0] <= adc_1_data_a[15: 0];
end
2'b10: begin
dma_1_wr <= ~dma_1_wr;
dma_1_data[63:48] <= adc_1_data_b[31:16];
dma_1_data[47:32] <= adc_1_data_b[15: 0];
dma_1_data[31:16] <= dma_1_data[63:48];
dma_1_data[15: 0] <= dma_1_data[47:32];
end
2'b01: begin
dma_1_wr <= ~dma_1_wr;
dma_1_data[63:48] <= adc_1_data_a[31:16];
dma_1_data[47:32] <= adc_1_data_a[15: 0];
dma_1_data[31:16] <= dma_1_data[63:48];
dma_1_data[15: 0] <= dma_1_data[47:32];
end
default: begin
dma_1_wr <= 1'b0;
dma_1_data[63:48] <= 16'd0;
dma_1_data[47:32] <= 16'd0;
dma_1_data[31:16] <= 16'd0;
dma_1_data[15: 0] <= 16'd0;
end
endcase
end
// instantiations
@ -210,52 +238,23 @@ module system_top (
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
.dt (gpio_t),
.di (gpio_o),
.do (gpio_i),
.dio ({ adc_irq, // 16
adc_fd, // 15
gpio_bd})); // 0
.dio (gpio_bd));
assign spi_adc_clk = spi_clk;
assign spi_clk_clk = spi_clk;
ad9625_fmc_spi i_ad9625_fmc_spi (
.spi_adc_csn (spi_adc_csn),
.spi_clk_csn (spi_clk_csn),
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_adc_sdio (spi_adc_sdio),
.spi_clk_sdio (spi_clk_sdio));
.spi_sdio (spi_sdio));
system_wrapper i_system_wrapper (
.DDR3_addr (DDR3_addr),
.DDR3_ba (DDR3_ba),
.DDR3_cas_n (DDR3_cas_n),
.DDR3_ck_n (DDR3_ck_n),
.DDR3_ck_p (DDR3_ck_p),
.DDR3_cke (DDR3_cke),
.DDR3_cs_n (DDR3_cs_n),
.DDR3_dm (DDR3_dm),
.DDR3_dq (DDR3_dq),
.DDR3_dqs_n (DDR3_dqs_n),
.DDR3_dqs_p (DDR3_dqs_p),
.DDR3_odt (DDR3_odt),
.DDR3_ras_n (DDR3_ras_n),
.DDR3_reset_n (DDR3_reset_n),
.DDR3_we_n (DDR3_we_n),
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
@ -280,8 +279,25 @@ module system_top (
.GPIO_I (gpio_i),
.GPIO_O (gpio_o),
.GPIO_T (gpio_t),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.adc_0_data_a (adc_0_data_a),
.adc_0_data_b (adc_0_data_b),
.adc_0_enable_a (adc_0_enable_a),
.adc_0_enable_b (adc_0_enable_b),
.adc_0_valid_a (),
.adc_0_valid_b (),
.adc_1_data_a (adc_1_data_a),
.adc_1_data_b (adc_1_data_b),
.adc_1_enable_a (adc_1_enable_a),
.adc_1_enable_b (adc_1_enable_b),
.adc_1_valid_a (),
.adc_1_valid_b (),
.adc_clk (adc_clk),
.dma_0_data (dma_0_data),
.dma_0_sync (1'b1),
.dma_0_wr (dma_0_wr),
.dma_1_data (dma_1_data),
.dma_1_sync (1'b1),
.dma_1_wr (dma_1_wr),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
@ -291,6 +307,9 @@ module system_top (
.iic_main_sda_io (iic_sda),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_gt_data (rx_gt_data),
.rx_gt_data_0 (rx_gt_data[63:0]),
.rx_gt_data_1 (rx_gt_data[127:64]),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
@ -298,8 +317,7 @@ module system_top (
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_0_o (spi_adc_csn),
.spi_csn_1_o (spi_clk_csn),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));