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up_tdd_cntrl: Fix memory map register writes

main
Istvan Csomortani 2016-11-01 10:06:57 +02:00
parent 9f4c5f8060
commit 5eff357568
1 changed files with 2 additions and 2 deletions
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4
library/common/up_tdd_cntrl.v
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@ -332,13 +332,13 @@ module up_tdd_cntrl (
up_tdd_tx_on_2 <= up_wdata[23:0]; up_tdd_tx_on_2 <= up_wdata[23:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_rx_off_2 <= up_wdata[23:0]; up_tdd_tx_off_2 <= up_wdata[23:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
up_tdd_rx_dp_on_2 <= up_wdata[23:0]; up_tdd_rx_dp_on_2 <= up_wdata[23:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
up_tdd_tx_dp_off_2 <= up_wdata[23:0]; up_tdd_rx_dp_off_2 <= up_wdata[23:0];
end end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
up_tdd_tx_dp_on_2 <= up_wdata[23:0]; up_tdd_tx_dp_on_2 <= up_wdata[23:0];