axi_jesd204_common/jesd204_up_common: Add event stats
Add statistics for : - number of link enable events - number of interrupt events (regardless of mask) 0x0B0 0x2C0 Stats Control Register [0] - Write 1 to clear stat registers 0x0B1 0x2C4 Link Enable Stat Register [15:0] Number of times the link was enabled from power-on or from last stat clear 0x0B4 0x2D0 IRQ Stat Register 0 [31:16] IRQ 1 counter [15:0] IRQ 0 counter 0x0B5 0x2D4 IRQ Stat Register 1 [31:16] IRQ 3 counter [15:0] IRQ 2 counter 0x0B6 0x2D8 IRQ Stat Register 2 [31:16] IRQ 5 counter [15:0] IRQ 4 counter 0x0B7 0x2DC IRQ Stat Register 3 [31:16] IRQ 7 counter [15:0] IRQ 6 countermain
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33f612091b
commit
5edc798b6b
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@ -54,7 +54,8 @@ module jesd204_up_common # (
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parameter MAX_OCTETS_PER_FRAME = 256,
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parameter NUM_IRQS = 1,
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parameter EXTRA_CFG_WIDTH = 1,
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parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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parameter ENABLE_LINK_STATS = 0
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) (
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input up_clk,
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input ext_resetn,
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@ -202,6 +203,54 @@ always @(posedge up_clk) begin
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end
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end
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/* Count link enable */
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wire [8*16-1:0] up_irq_event_cnt_bus;
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wire [15:0] up_link_enable_cnt_s;
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genvar i;
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generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats
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reg [15:0] up_link_enable_cnt = 'h0;
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reg up_reset_core_d1 = 'b1;
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wire up_stat_clear;
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assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]);
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always @(posedge up_clk) begin
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up_reset_core_d1 <= up_reset_core;
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if (up_stat_clear) begin
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up_link_enable_cnt <= 'h0;
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end else begin
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if (~up_reset_core & up_reset_core_d1) begin
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up_link_enable_cnt <= up_link_enable_cnt + 16'd1;
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end
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end
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end
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assign up_link_enable_cnt_s = up_link_enable_cnt;
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/* Count IRQ events for max 8 interrupt sources */
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for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt
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reg [15:0] up_irq_event_cnt = 'h0;
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always @(posedge up_clk) begin
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if (up_stat_clear) begin
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up_irq_event_cnt <= 'h0;
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end else if (up_irq_trigger[i]) begin
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up_irq_event_cnt <= up_irq_event_cnt + 16'd1;
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end
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end
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assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt;
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end
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end else begin : g_no_link_stats
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assign up_irq_event_cnt_bus = 'h0;
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assign up_link_enable_cnt_s = 'h0;
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end
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endgenerate
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wire [20:0] clk_mon_count;
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@ -250,6 +299,14 @@ always @(*) begin
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/* 0x90-0x9f reserved for core specific configuration options */
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/* 0xb0 Stat control */
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12'h0b1: up_rdata <= up_link_enable_cnt_s;
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/* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
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12'h0b4: up_rdata <= up_irq_event_cnt_bus[0*32 +: 32];
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12'h0b5: up_rdata <= up_irq_event_cnt_bus[1*32 +: 32];
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12'h0b6: up_rdata <= up_irq_event_cnt_bus[2*32 +: 32];
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12'h0b7: up_rdata <= up_irq_event_cnt_bus[3*32 +: 32];
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default: up_rdata <= 'h00;
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endcase
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end
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@ -48,7 +48,8 @@ module axi_jesd204_rx #(
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parameter ID = 0,
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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parameter ENABLE_LINK_STATS = 0
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) (
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input s_axi_aclk,
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input s_axi_aresetn,
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@ -204,7 +205,8 @@ jesd204_up_common #(
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
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.NUM_IRQS(5),
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.EXTRA_CFG_WIDTH(27),
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.LINK_MODE(LINK_MODE)
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.LINK_MODE(LINK_MODE),
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.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
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) i_up_common (
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.up_clk(s_axi_aclk),
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.ext_resetn(s_axi_aresetn),
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@ -48,7 +48,8 @@ module axi_jesd204_tx #(
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parameter ID = 0,
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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parameter ENABLE_LINK_STATS = 0
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) (
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input s_axi_aclk,
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input s_axi_aresetn,
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@ -181,7 +182,8 @@ jesd204_up_common #(
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.NUM_IRQS(5),
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.EXTRA_CFG_WIDTH(21),
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.MAX_OCTETS_PER_FRAME(8),
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.LINK_MODE(LINK_MODE)
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.LINK_MODE(LINK_MODE),
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.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
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) i_up_common (
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.up_clk(s_axi_aclk),
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.ext_resetn(s_axi_aresetn),
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Reference in New Issue