axi_jesd204_common/jesd204_up_common: Add event stats

Add statistics for :
 - number of link enable events
 - number of interrupt events (regardless of mask)

0x0B0 0x2C0 Stats Control Register
  [0] - Write 1 to clear stat registers

0x0B1 0x2C4 Link Enable Stat Register
  [15:0] Number of times the link was enabled from power-on or from last
         stat clear

0x0B4 0x2D0 IRQ Stat Register 0
  [31:16] IRQ 1 counter
  [15:0]  IRQ 0 counter

0x0B5 0x2D4 IRQ Stat Register 1
  [31:16] IRQ 3 counter
  [15:0]  IRQ 2 counter

0x0B6 0x2D8 IRQ Stat Register 2
  [31:16] IRQ 5 counter
  [15:0]  IRQ 4 counter

0x0B7 0x2DC IRQ Stat Register 3
  [31:16] IRQ 7 counter
  [15:0]  IRQ 6 counter
main
Laszlo Nagy 2020-09-02 09:45:39 +01:00 committed by Laszlo Nagy
parent 33f612091b
commit 5edc798b6b
3 changed files with 66 additions and 5 deletions

View File

@ -54,7 +54,8 @@ module jesd204_up_common # (
parameter MAX_OCTETS_PER_FRAME = 256,
parameter NUM_IRQS = 1,
parameter EXTRA_CFG_WIDTH = 1,
parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter ENABLE_LINK_STATS = 0
) (
input up_clk,
input ext_resetn,
@ -202,6 +203,54 @@ always @(posedge up_clk) begin
end
end
/* Count link enable */
wire [8*16-1:0] up_irq_event_cnt_bus;
wire [15:0] up_link_enable_cnt_s;
genvar i;
generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats
reg [15:0] up_link_enable_cnt = 'h0;
reg up_reset_core_d1 = 'b1;
wire up_stat_clear;
assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]);
always @(posedge up_clk) begin
up_reset_core_d1 <= up_reset_core;
if (up_stat_clear) begin
up_link_enable_cnt <= 'h0;
end else begin
if (~up_reset_core & up_reset_core_d1) begin
up_link_enable_cnt <= up_link_enable_cnt + 16'd1;
end
end
end
assign up_link_enable_cnt_s = up_link_enable_cnt;
/* Count IRQ events for max 8 interrupt sources */
for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt
reg [15:0] up_irq_event_cnt = 'h0;
always @(posedge up_clk) begin
if (up_stat_clear) begin
up_irq_event_cnt <= 'h0;
end else if (up_irq_trigger[i]) begin
up_irq_event_cnt <= up_irq_event_cnt + 16'd1;
end
end
assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt;
end
end else begin : g_no_link_stats
assign up_irq_event_cnt_bus = 'h0;
assign up_link_enable_cnt_s = 'h0;
end
endgenerate
wire [20:0] clk_mon_count;
@ -250,6 +299,14 @@ always @(*) begin
/* 0x90-0x9f reserved for core specific configuration options */
/* 0xb0 Stat control */
12'h0b1: up_rdata <= up_link_enable_cnt_s;
/* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */
12'h0b4: up_rdata <= up_irq_event_cnt_bus[0*32 +: 32];
12'h0b5: up_rdata <= up_irq_event_cnt_bus[1*32 +: 32];
12'h0b6: up_rdata <= up_irq_event_cnt_bus[2*32 +: 32];
12'h0b7: up_rdata <= up_irq_event_cnt_bus[3*32 +: 32];
default: up_rdata <= 'h00;
endcase
end

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@ -48,7 +48,8 @@ module axi_jesd204_rx #(
parameter ID = 0,
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter ENABLE_LINK_STATS = 0
) (
input s_axi_aclk,
input s_axi_aresetn,
@ -204,7 +205,8 @@ jesd204_up_common #(
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
.NUM_IRQS(5),
.EXTRA_CFG_WIDTH(27),
.LINK_MODE(LINK_MODE)
.LINK_MODE(LINK_MODE),
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
) i_up_common (
.up_clk(s_axi_aclk),
.ext_resetn(s_axi_aresetn),

View File

@ -48,7 +48,8 @@ module axi_jesd204_tx #(
parameter ID = 0,
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
parameter LINK_MODE = 1 // 2 - 64B/66B; 1 - 8B/10B
parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
parameter ENABLE_LINK_STATS = 0
) (
input s_axi_aclk,
input s_axi_aresetn,
@ -181,7 +182,8 @@ jesd204_up_common #(
.NUM_IRQS(5),
.EXTRA_CFG_WIDTH(21),
.MAX_OCTETS_PER_FRAME(8),
.LINK_MODE(LINK_MODE)
.LINK_MODE(LINK_MODE),
.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
) i_up_common (
.up_clk(s_axi_aclk),
.ext_resetn(s_axi_aresetn),