jesd204_rx: Generate interrupt on frame alignment error

When frame alignment error monitoring is enabled and error threshold is met
at least for one lane, generate an interrupt so software can reset the link and
do further bring-up steps.

library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v

@@ -98,6 +98,7 @@ module axi_jesd204_rx #(
 
   input core_event_sysref_alignment_error,
   input core_event_sysref_edge,
+  input core_event_frame_alignment_error,
 
   output [6:0] core_ctrl_err_statistics_mask,
   output core_ctrl_err_statistics_reset,
@@ -131,7 +132,7 @@ wire [31:0] up_rdata_common;
 wire [31:0] up_rdata_sysref;
 wire [31:0] up_rdata_rx;
 
-wire [4:0] up_irq_trigger = 5'b00000;
+wire [4:0] up_irq_trigger;
 
 wire up_cfg_is_writeable;
 wire up_cfg_sysref_oneshot;
@@ -143,6 +144,16 @@ wire [7:0] up_cfg_frame_align_err_threshold;
 
 wire up_reset;
 wire up_reset_synchronizer;
+wire up_event_frame_alignment_error;
+
+sync_event i_sync_frame_align_err (
+  .in_clk(core_clk),
+  .in_event(core_event_frame_alignment_error),
+  .out_clk(s_axi_aclk),
+  .out_event(up_event_frame_alignment_error)
+);
+
+assign up_irq_trigger = {4'b0,up_event_frame_alignment_error};
 
 up_axi #(
   .AXI_ADDRESS_WIDTH (14)

library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc

@@ -84,6 +84,18 @@ set_false_path \
   -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
   -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
 
+set_false_path \
+  -from [get_pins {i_sync_frame_align_err/in_toggle_d1_reg/C}] \
+  -to [get_pins {i_sync_frame_align_err/i_sync_out/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_sync_frame_align_err/out_toggle_d1_reg/C}] \
+  -to [get_pins {i_sync_frame_align_err/i_sync_in/cdc_sync_stage1_reg[0]/D}]
+
+set_false_path \
+  -from [get_pins {i_sync_frame_align_err/cdc_hold_reg*/C}] \
+  -to [get_pins {i_sync_frame_align_err/out_event_reg*/D}]
+
 # Don't place them too far appart
 set_max_delay -datapath_only \
   -from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \

library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl

@@ -106,6 +106,7 @@ adi_add_bus "rx_event" "slave" \
   { \
     { "core_event_sysref_alignment_error" "sysref_alignment_error" } \
     { "core_event_sysref_edge" "sysref_edge" } \
+    { "core_event_frame_alignment_error" "frame_alignment_error" } \
   }
 
 adi_add_bus "rx_status" "slave" \

library/jesd204/interfaces/interfaces_ip.tcl

@@ -110,3 +110,4 @@ adi_if_ports input -1 data
 adi_if_define "jesd204_rx_event"
 adi_if_ports output 1 sysref_alignment_error
 adi_if_ports output 1 sysref_edge
+adi_if_ports output 1 frame_alignment_error

library/jesd204/jesd204_rx/jesd204_rx.v

@@ -70,6 +70,7 @@ module jesd204_rx #(
 
   output event_sysref_alignment_error,
   output event_sysref_edge,
+  output event_frame_alignment_error,
 
   output [NUM_LINKS-1:0] sync,
 
@@ -173,6 +174,7 @@ wire [2*NUM_LANES-1:0] frame_align;
 wire [NUM_LANES-1:0] ifs_ready;
 
 reg [NUM_LANES-1:0] frame_align_err_thresh_met = {NUM_LANES{1'b0}};
+reg [NUM_LANES-1:0] event_frame_alignment_error_per_lane = {NUM_LANES{1'b0}};
 
 reg buffer_release_opportunity = 1'b0;
 
@@ -383,14 +385,20 @@ for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
     .status_frame_align_err_cnt(status_lane_frame_align_err_cnt[8*i+7:8*i])
   );
 
-  if(ENABLE_FRAME_ALIGN_CHECK && ENABLE_FRAME_ALIGN_ERR_RESET) begin : gen_frame_align_err_thresh
+  if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align_err_thresh
     always @(posedge clk) begin
-      frame_align_err_thresh_met[i] <= status_lane_frame_align_err_cnt[8*i+7:8*i] >= cfg_frame_align_err_threshold;
+      if (status_lane_frame_align_err_cnt[8*i+7:8*i] >= cfg_frame_align_err_threshold) begin
+        frame_align_err_thresh_met[i] <= 1'b1;
+        event_frame_alignment_error_per_lane[i] <= ~frame_align_err_thresh_met[i];
+      end else begin
+        frame_align_err_thresh_met[i] <= 1'b0;
+        event_frame_alignment_error_per_lane[i] <= 1'b0;
+      end
     end
   end
 end
 
-
+assign event_frame_alignment_error = |event_frame_alignment_error_per_lane;
 
 /* Delay matching based on the number of pipeline stages */
 reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0;
@@ -503,6 +511,7 @@ assign ilas_config_addr = 'b0;
 assign ilas_config_data = 'b0;
 assign status_lane_cgs_state = 'b0;
 assign status_lane_ifs_ready = {NUM_LANES{1'b1}};
+assign event_frame_alignment_error = 1'b0;
 
 end
 

library/jesd204/jesd204_rx/jesd204_rx_ip.tcl

@@ -143,6 +143,7 @@ adi_add_bus "rx_event" "master" \
   { \
     { "event_sysref_alignment_error" "sysref_alignment_error" } \
     { "event_sysref_edge" "sysref_edge" } \
+    { "event_frame_alignment_error" "frame_alignment_error" } \
   }
 
 adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status:rx_data" "reset"