diff --git a/library/axi_i2s_adi/fifo_synchronizer.vhd b/library/axi_i2s_adi/fifo_synchronizer.vhd
index b33bf648c..336e74d9a 100644
--- a/library/axi_i2s_adi/fifo_synchronizer.vhd
+++ b/library/axi_i2s_adi/fifo_synchronizer.vhd
@@ -63,7 +63,7 @@ architecture impl of fifo_synchronizer is
 	signal rd_addr : natural range 0 to DEPTH - 1;
 	signal wr_addr : natural range 0 to DEPTH - 1;
 
-	signal cdc_sync_stage0_tick : std_logic;
+	signal cdc_sync_stage0_tick : std_logic := '0';
 	signal cdc_sync_stage1_tick : std_logic;
 	signal cdc_sync_stage2_tick : std_logic;
 	signal cdc_sync_stage3_tick : std_logic;
diff --git a/library/axi_i2s_adi/i2s_controller.vhd b/library/axi_i2s_adi/i2s_controller.vhd
index af11e74a2..9eb439bb7 100644
--- a/library/axi_i2s_adi/i2s_controller.vhd
+++ b/library/axi_i2s_adi/i2s_controller.vhd
@@ -83,7 +83,7 @@ constant NUM_RX			: integer := C_HAS_RX * C_NUM_CH;
 
 signal enable			: Boolean;
 
-signal cdc_sync_stage0_tick	: std_logic;
+signal cdc_sync_stage0_tick	: std_logic := '0';
 signal cdc_sync_stage1_tick	: std_logic;
 signal cdc_sync_stage2_tick	: std_logic;
 signal cdc_sync_stage3_tick	: std_logic;