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axi_clkgen: Added phase related parameters

main
Adrian Costina 2015-12-02 18:50:23 +02:00
parent 6e549171f0
commit 5cf45b2978
2 changed files with 11 additions and 5 deletions
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6
library/axi_clkgen/axi_clkgen.v
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@ -76,7 +76,9 @@ module axi_clkgen (
parameter VCO_DIV = 11;
parameter VCO_MUL = 49;
parameter CLK0_DIV = 6;
parameter CLK0_PHASE = 0.000;
parameter CLK1_DIV = 6;
parameter CLK1_PHASE = 0.000;
// clocks
@ -200,7 +202,9 @@ module axi_clkgen (
.MMCM_VCO_DIV (VCO_DIV),
.MMCM_VCO_MUL (VCO_MUL),
.MMCM_CLK0_DIV (CLK0_DIV),
.MMCM_CLK1_DIV (CLK1_DIV))
.MMCM_CLK0_PHASE (CLK0_PHASE),
.MMCM_CLK1_DIV (CLK1_DIV),
.MMCM_CLK1_PHASE (CLK1_PHASE))
i_mmcm_drp (
.clk (clk),
.clk2 (clk2),

10
library/common/ad_mmcm_drp.v
View File

@ -72,7 +72,9 @@ module ad_mmcm_drp (
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK0_PHASE = 0.000 ;
parameter MMCM_CLK1_DIV = 6;
parameter MMCM_CLK1_PHASE = 0.000;
// clocks
@ -143,11 +145,11 @@ module ad_mmcm_drp (
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
@ -200,11 +202,11 @@ module ad_mmcm_drp (
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),