zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cn0501: Initial commit for Coraz7s

main
sergiu arpadi 2020-08-14 15:55:42 +03:00 committed by sarpadi
parent 71009e74ff
commit 5c87e5b1a7
6 changed files with 416 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

129
projects/cn0501/common/cn0501_bd.tcl Normal file
View File

@ -0,0 +1,129 @@
# ad7768 interface
create_bd_port -dir I adc_clk
create_bd_port -dir I adc_valid
create_bd_port -dir I adc_valid_pp
create_bd_port -dir I adc_sync
create_bd_port -dir I -from 31 -to 0 adc_data
create_bd_port -dir I -from 31 -to 0 adc_data_0
create_bd_port -dir I -from 31 -to 0 adc_data_1
create_bd_port -dir I -from 31 -to 0 adc_data_2
create_bd_port -dir I -from 31 -to 0 adc_data_3
create_bd_port -dir I -from 31 -to 0 adc_data_4
create_bd_port -dir I -from 31 -to 0 adc_data_5
create_bd_port -dir I -from 31 -to 0 adc_data_6
create_bd_port -dir I -from 31 -to 0 adc_data_7
create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t
create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io
# instances
ad_ip_instance axi_dmac ad7768_dma
ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter ad7768_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter ad7768_dma CONFIG.CYCLIC 0
ad_ip_parameter ad7768_dma CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter ad7768_dma CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter ad7768_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter ad7768_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_instance axi_dmac ad7768_dma_2
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter ad7768_dma_2 CONFIG.CYCLIC 0
ad_ip_parameter ad7768_dma_2 CONFIG.SYNC_TRANSFER_START 1
ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter ad7768_dma_2 CONFIG.AXI_SLICE_DEST 0
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter ad7768_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 256
# ps7-hp1
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1
# gpio
ad_ip_instance axi_gpio ad7768_gpio
ad_ip_parameter ad7768_gpio CONFIG.C_IS_DUAL 1
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO2_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1
#i2c
ad_ip_instance axi_iic axi_iic_0
# adc-path channel pack
ad_ip_instance util_cpack2 util_ad7768_adc_pack
ad_ip_parameter util_ad7768_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter util_ad7768_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
ad_connect adc_clk util_ad7768_adc_pack/clk
ad_connect sys_rstgen/peripheral_reset util_ad7768_adc_pack/reset
ad_connect adc_valid_pp util_ad7768_adc_pack/fifo_wr_en
for {set i 0} {$i < 8} {incr i} {
ad_connect adc_data_$i util_ad7768_adc_pack/fifo_wr_data_$i
}
# axi_generic_adc
ad_ip_instance axi_generic_adc axi_ad7768_adc
ad_ip_parameter axi_ad7768_adc CONFIG.NUM_OF_CHANNELS 8
for {set i 0} {$i < 8} {incr i} {
ad_ip_instance xlslice xlslice_$i
set_property -dict [list CONFIG.DIN_FROM $i CONFIG.DIN_WIDTH {8} CONFIG.DOUT_WIDTH {1} CONFIG.DIN_TO $i] [get_bd_cells xlslice_$i]
ad_connect axi_ad7768_adc/adc_enable xlslice_$i/Din
ad_connect xlslice_$i/Dout util_ad7768_adc_pack/enable_$i
}
# interconnects
ad_connect adc_clk ad7768_dma/fifo_wr_clk
ad_connect adc_valid ad7768_dma/fifo_wr_en
ad_connect adc_sync ad7768_dma/fifo_wr_sync
ad_connect adc_data ad7768_dma/fifo_wr_din
ad_connect adc_clk ad7768_dma_2/fifo_wr_clk
ad_connect sys_cpu_resetn ad7768_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn ad7768_dma_2/m_dest_axi_aresetn
ad_connect util_ad7768_adc_pack/packed_fifo_wr ad7768_dma_2/fifo_wr
ad_connect util_ad7768_adc_pack/fifo_wr_overflow axi_ad7768_adc/adc_dovf
ad_connect adc_clk axi_ad7768_adc/adc_clk
ad_connect sys_ps7/FCLK_CLK0 axi_ad7768_adc/s_axi_aclk
ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i
ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o
ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t
ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i
ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o
ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t
ad_connect iic_0_io axi_iic_0/iic
# interrupts
ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq
ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt
ad_cpu_interrupt ps-11 mb-11 axi_iic_0/iic2intc_irpt
ad_cpu_interrupt ps-10 mb-10 ad7768_dma_2/irq
# cpu / memory interconnects
ad_cpu_interconnect 0x7C400000 ad7768_dma
ad_cpu_interconnect 0x7C420000 ad7768_gpio
ad_cpu_interconnect 0x7C440000 axi_iic_0
ad_cpu_interconnect 0x7C480000 ad7768_dma_2
ad_cpu_interconnect 0x43c00000 axi_ad7768_adc
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp0_interconnect sys_cpu_clk ad7768_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma_2/m_dest_axi

21
projects/cn0501/coraz7s/Makefile Normal file
View File

@ -0,0 +1,21 @@
####################################################################################
## Copyright 2019-2020(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := cn0501_coraz7s
M_DEPS += ../common/cn0501_bd.tcl
M_DEPS += ../../ad7768evb/common/ad7768_if.v
M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += axi_generic_adc
LIB_DEPS += util_pack/util_cpack2
include ../../scripts/project-xilinx.mk

13
projects/cn0501/coraz7s/system_bd.tcl Normal file
View File

@ -0,0 +1,13 @@
source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring
#set sys_dma_clk [get_bd_nets sys_dma_clk]
source ../common/cn0501_bd.tcl

22
projects/cn0501/coraz7s/system_constr.xdc Normal file
View File

@ -0,0 +1,22 @@
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports clk_in] ; ## IO8
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ready_in] ; ## IO9
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports data_in[0]] ; ## IO7
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports data_in[1]] ; ## IO6
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports data_in[2]] ; ## IO5
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports data_in[3]] ; ## IO4
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports data_in[4]] ; ## IO3
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports data_in[5]] ; ## IO2
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports data_in[6]] ; ## IO1
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports data_in[7]] ; ## IO0
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports spi_csn] ; ## IO10
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk] ; ## IO13
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi] ; ## IO11
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso] ; ## IO12
set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_sda]
create_clock -name adc_clk -period 20 [get_ports clk_in]

15
projects/cn0501/coraz7s/system_project.tcl Normal file
View File

@ -0,0 +1,15 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project cn0501_coraz7s
adi_project_files cn0501_coraz7s [list \
"$ad_hdl_dir/projects/ad7768evb/common/ad7768_if.v" \
"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc" \
"system_top.v" \
"system_constr.xdc" \
]
adi_project_run cn0501_coraz7s

216
projects/cn0501/coraz7s/system_top.v Normal file
View File

@ -0,0 +1,216 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [1:0] btn,
inout [5:0] led,
inout iic_scl,
inout iic_sda,
input clk_in,
input ready_in,
input [ 7:0] data_in,
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire adc_clk;
wire adc_valid;
wire adc_valid_pp;
wire adc_sync;
wire [31:0] adc_data;
wire [31:0] adc_data_0;
wire [31:0] adc_data_1;
wire [31:0] adc_data_2;
wire [31:0] adc_data_3;
wire [31:0] adc_data_4;
wire [31:0] adc_data_5;
wire [31:0] adc_data_6;
wire [31:0] adc_data_7;
wire up_sshot;
wire [ 1:0] up_format;
wire up_crc_enable;
wire up_crc_4_or_16_n;
wire [63:0] adc_gpio_i;
wire [63:0] adc_gpio_o;
wire [63:0] adc_gpio_t;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// use crystal
assign up_sshot = gpio_o[36];
assign up_format = gpio_o[35:34];
assign up_crc_enable = gpio_o[33];
assign up_crc_4_or_16_n = gpio_o[32];
// instantiations
assign gpio_i[36:32] = 5'b0;
assign gpio_i[39:37] = gpio_o[39:37];
assign gpio_i[47:44] = gpio_o[47:44];
assign gpio_i[63:53] = gpio_o[63:53];
ad7768_if i_ad7768_if (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_valid_pp (adc_valid_pp),
.adc_sync (adc_sync),
.adc_data (adc_data),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.up_sshot (up_sshot),
.up_format (up_format),
.up_crc_enable (up_crc_enable),
.up_crc_4_or_16_n (up_crc_4_or_16_n),
.up_status_clr (adc_gpio_o[32:0]),
.up_status (adc_gpio_i[32:0]));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.adc_gpio_0_i (adc_gpio_i[31:0]),
.adc_gpio_0_o (adc_gpio_o[31:0]),
.adc_gpio_0_t (adc_gpio_t[31:0]),
.adc_gpio_1_i (adc_gpio_i[63:32]),
.adc_gpio_1_o (adc_gpio_o[63:32]),
.adc_gpio_1_t (adc_gpio_t[63:32]),
.adc_valid (adc_valid),
.adc_valid_pp (adc_valid_pp),
.adc_sync (adc_sync),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.iic_0_io_scl_io (iic_scl),
.iic_0_io_sda_io (iic_sda),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk),
.spi0_csn_0_o (spi_csn),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************