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common/ad_mux: Pipelined mux, rtl and TB 

Build a large mux from smaller ones defined by the REQ_MUX_SZ parameter
 Use EN_REG to add a register at the output of the small muxes to help
 timing closure.
main
Laszlo Nagy 2020-03-18 14:19:07 +01:00 committed by Laszlo Nagy
parent 1c71815bd7
commit 5c561665b0
6 changed files with 373 additions and 0 deletions
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
// Constraints : CH_CNT must be power of 2
// Build a large mux from smaller ones defined by the MUX_SZ parameter
// Use EN_REG to add a register at the output of the small muxes to help
// timing closure.
module ad_mux #(
parameter CH_W = 16, // Width of input channel
parameter CH_CNT = 64, // Number of input channels
parameter REQ_MUX_SZ = 8, // Size of mux which acts as a building block
parameter EN_REG = 1, // Enable register at output of each mux
parameter DW = CH_W*CH_CNT
) (
input clk,
input [DW-1:0] data_in,
input [$clog2(CH_CNT)-1:0] ch_sel,
output [CH_W-1:0] data_out
);
localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
localparam CLOG2_CH_CNT = $clog2(CH_CNT);
localparam CLOG2_MUX_SZ = $clog2(MUX_SZ);
localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ);
wire [NUM_STAGES*DW+CH_W-1:0] mux_in;
wire [NUM_STAGES*CLOG2_CH_CNT-1:0] ch_sel_pln;
assign mux_in[DW-1:0] = data_in;
assign ch_sel_pln[CLOG2_CH_CNT-1:0] = ch_sel;
genvar i;
genvar j;
generate
for (i = 0; i < NUM_STAGES; i = i + 1) begin: g_stage
wire [CLOG2_CH_CNT-1:0] ch_sel_cur;
assign ch_sel_cur = ch_sel_pln[i*CLOG2_CH_CNT+:CLOG2_CH_CNT];
wire [CLOG2_MUX_SZ-1:0] ch_sel_w;
assign ch_sel_w = ch_sel_cur >> i*CLOG2_MUX_SZ;
if (EN_REG) begin
reg [CLOG2_CH_CNT-1:0] ch_sel_d;
always @(posedge clk) begin
ch_sel_d <= ch_sel_cur;
end
if (i<NUM_STAGES-1) begin
assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_d;
end
end else begin
if (i<NUM_STAGES-1) begin
assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_cur;
end
end
for (j = 0; j < MUX_SZ**(NUM_STAGES-i); j = j + MUX_SZ) begin: g_mux
ad_mux_core #(
.CH_W (CH_W),
.CH_CNT (MUX_SZ),
.EN_REG (EN_REG)
) i_mux (
.clk (clk),
.data_in (mux_in[i*DW+j*CH_W+:MUX_SZ*CH_W]),
.ch_sel (ch_sel_w),
.data_out (mux_in[(i+1)*DW+(j/MUX_SZ)*CH_W+:CH_W])
);
end
end
endgenerate
assign data_out = mux_in[NUM_STAGES*DW+:CH_W];
endmodule

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library/common/ad_mux_core.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mux_core #(
parameter CH_W = 16,
parameter CH_CNT = 8,
parameter EN_REG = 0
) (
input clk,
input [CH_W*CH_CNT-1:0] data_in,
input [$clog2(CH_CNT)-1:0] ch_sel,
output [CH_W-1:0] data_out
);
wire [CH_W-1:0] data_out_loc;
assign data_out_loc = data_in >> CH_W*ch_sel;
generate if (EN_REG) begin
reg [CH_W-1:0] data_out_reg;
always @(posedge clk) begin
data_out_reg <= data_out_loc;
end
assign data_out = data_out_reg;
end else begin
assign data_out = data_out_loc;
end
endgenerate
endmodule

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#!/bin/bash
SOURCE="ad_mux_tb.v"
SOURCE+=" ../ad_mux.v"
SOURCE+=" ../ad_mux_core.v"
cd `dirname $0`
source run_tb.sh

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`timescale 1ns/100ps
module ad_mux_tb;
parameter VCD_FILE = "ad_mux_tb.vcd";
parameter CH_W = 16; // Width of input channel
parameter CH_CNT = 64; // Number of input channels
parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block
parameter EN_REG = 1; // Enable register at output of each mux
localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ);
localparam DW = CH_W*CH_CNT;
`include "tb_base.v"
reg [CH_W*CH_CNT-1:0] data_in = 'h0;
reg [$clog2(CH_CNT)-1:0] ch_sel = 'h0;
wire [CH_W-1:0] data_out;
ad_mux #(
.CH_W(CH_W),
.CH_CNT(CH_CNT),
.REQ_MUX_SZ(REQ_MUX_SZ),
.EN_REG(EN_REG)
) DUT (
.clk(clk),
.data_in(data_in),
.ch_sel(ch_sel),
.data_out(data_out)
);
wire [CH_W-1:0] ref_data;
generate
if (EN_REG) begin
integer ii;
reg [CH_W*CH_CNT-1:0] mux_pln [1:NUM_STAGES];
always @(posedge clk) begin
mux_pln[1] <= data_in >> ch_sel*CH_W;
for (ii=2; ii<=NUM_STAGES; ii=ii+1) begin
mux_pln[ii] <= mux_pln[ii-1];
end
end
assign ref_data = mux_pln[NUM_STAGES];
end else begin
assign ref_data = data_in >> ch_sel*CH_W;
end
endgenerate
integer i;
initial begin
for (i=0; i<CH_W*CH_CNT/8; i=i+1) begin
data_in[i*8+:8] = i[7:0];
end
for (i=0; i<CH_CNT; i=i+1) begin
@(posedge clk);
ch_sel <= ch_sel + 1;
end
end
wire mismatch;
assign mismatch = ref_data !== data_out;
always @(posedge clk) begin
if (mismatch) begin
failed <= 1'b1;
end
end
endmodule

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NAME=`basename $0`
case "$SIMULATOR" in
modelsim)
# ModelSim flow
vlib work
vlog ${SOURCE} || exit 1
vsim ${NAME} -do "add log /* -r; run -a" -gui || exit 1
;;
xsim)
# xsim flow
xvlog -log ${NAME}_xvlog.log --sourcelibdir . ${SOURCE}
xelab -log ${NAME}_xelab.log -debug all ${NAME}
xsim work.${NAME} -R
;;
*)
mkdir -p run
mkdir -p vcd
iverilog ${SOURCE} -o run/run_${NAME} $1 || exit 1
cd vcd
../run/run_${NAME}
;;
esac

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//
// The ADI JESD204 Core is released under the following license, which is
// different than all other HDL cores in this repository.
//
// Please read this, and understand the freedoms and responsibilities you have
// by using this source code/core.
//
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
//
// This core is free software, you can use run, copy, study, change, ask
// questions about and improve this core. Distribution of source, or resulting
// binaries (including those inside an FPGA or ASIC) require you to release the
// source of the entire project (excluding the system libraries provide by the
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License version 2
// along with this source code, and binary. If not, see
// <http://www.gnu.org/licenses/>.
//
// Commercial licenses (with commercial support) of this JESD204 core are also
// available under terms different than the General Public License. (e.g. they
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
// core with any corresponding source code.) For these alternate terms you must
// purchase a license from Analog Devices Technology Licensing Office. Users
// interested in such a license should contact jesd204-licensing@analog.com for
// more information. This commercial license is sub-licensable (if you purchase
// chips from Analog Devices, incorporate them into your PCB level product, and
// purchase a JESD204 license, end users of your product will also have a
// license to use this core in a commercial setting without releasing their
// source code).
//
// In addition, we kindly ask you to acknowledge ADI in any program, application
// or publication in which you use this JESD204 HDL core. (You are not required
// to do so; it is up to your common sense to decide whether you want to comply
// with this request or not.) For general publications, we suggest referencing :
// “The design and implementation of the JESD204 HDL Core used in this project
// is copyright © 2016-2017, Analog Devices, Inc.”
//
reg clk = 1'b0;
reg [3:0] reset_shift = 4'b1111;
reg trigger_reset = 1'b0;
wire reset;
reg failed = 1'b0;
initial
begin
$dumpfile (VCD_FILE);
$dumpvars;
`ifdef TIMEOUT
#`TIMEOUT
`else
#100000
`endif
if (failed == 1'b0)
$display("SUCCESS");
else
$display("FAILED");
$finish;
end
always @(*) #10 clk <= ~clk;
always @(posedge clk) begin
if (trigger_reset == 1'b1) begin
reset_shift <= 3'b111;
end else begin
reset_shift <= {reset_shift[2:0],1'b0};
end
end
assign reset = reset_shift[3];
task do_trigger_reset;
begin
@(posedge clk) trigger_reset <= 1'b1;
@(posedge clk) trigger_reset <= 1'b0;
end
endtask