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ad_ip_jesd204_tpl_dac: Drop extra pipeline stage from the framer 

All the inputs to the framer are registered. And the framer itself does not
have any combinatorial logic, it just re-orders the wire numbering of the
individual bits.

Currently the framer module adds a output register stage, but since there
is no logic in the framer this just means that these registers are directly
connected to the output of the previous register stage.

Remove the extra pipeline register. This slightly reduces utilization and
pipeline delay of the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-08-03 09:00:41 +02:00 committed by Lars-Peter Clausen
parent 20ee9b8d2a
commit 5af80e79b3
1 changed files with 2 additions and 13 deletions
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15
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
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@ -43,17 +43,6 @@ module ad_ip_jesd204_tpl_dac_framer #(
localparam HD = NUM_LANES > NUM_CHANNELS ? 1 : 0;
localparam OCT_OFFSET = HD ? 32 : 8;
// internal registers
reg [NUM_LANES*32-1:0] link_data_r = 'd0;
wire [NUM_LANES*32-1:0] link_data_s;
always @(posedge clk) begin
link_data_r <= link_data_s;
end
assign link_data = link_data_r;
generate
genvar i;
genvar j;
@ -64,8 +53,8 @@ module ad_ip_jesd204_tpl_dac_framer #(
localparam oct0_lsb = HD ? ((i * H + j % H) * 64 + (j / H) * 8) : (k * 16);
localparam oct1_lsb = oct0_lsb + OCT_OFFSET;
assign link_data_s[oct0_lsb+:8] = dac_data[dac_lsb+8+:8];
assign link_data_s[oct1_lsb+:8] = dac_data[dac_lsb+:8];
assign link_data[oct0_lsb+:8] = dac_data[dac_lsb+8+:8];
assign link_data[oct1_lsb+:8] = dac_data[dac_lsb+:8];
end
end
endgenerate