axi_dmac: Generate per core instance constraint file
When having multiple DMA cores sharing the same constraint file Vivado seems to apply the constraints from the first core to all the other cores when re-running synthesis and implementation from within the Vivado GUI. This causes wrong timing constraints if the DMA cores have different configurations. To avoid this issue use a TTCL template that generates a custom constraint file for each DMA core instance. This also allows us to drop the asynchronous clock detection hack from the constraint file and move it to the template and only generate the CDC constraints if the clock domains are asynchronous. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
Lars-Peter Clausen
parent
522f30ce21
commit
5af371db6b
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@ -26,7 +26,7 @@ M_DEPS += src_fifo_inf.v
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M_DEPS += splitter.v
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M_DEPS += response_generator.v
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M_DEPS += axi_dmac.v
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M_DEPS += axi_dmac_constr.xdc
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M_DEPS += axi_dmac_constr.ttcl
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M_DEPS += ../util_axis_resize/util_axis_resize.xpr
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M_DEPS += ../util_axis_fifo/util_axis_fifo.xpr
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@ -0,0 +1,164 @@
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<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set async_dest_req [getBooleanValue "C_CLKS_ASYNC_DEST_REQ"] :>
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<: set async_req_src [getBooleanValue "C_CLKS_ASYNC_REQ_SRC"] :>
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<: set async_src_dest [getBooleanValue "C_CLKS_ASYNC_SRC_DEST"] :>
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set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
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set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
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[get_cells -quiet -hier *cdc_sync_stage2_reg*]
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<: if {$async_req_src} { :>
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $req_clk]
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set_false_path -quiet \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $src_clk \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *eot_mem_reg* \
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-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
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-to $src_clk \
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[get_property -min PERIOD $src_clk]
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<: } :>
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<: if {$async_dest_req} { :>
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $dest_clk]
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set_false_path -quiet \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $req_clk \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *eot_mem_reg* \
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-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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<: } :>
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<: if {$async_src_dest} { :>
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property -min PERIOD $dest_clk]
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# Not sure why, but it seems the built-in constraints for the RAM36B are wrong
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \
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[get_property -min PERIOD $dest_clk]
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<: } :>
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# Reset signals
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set_false_path -quiet \
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-from $req_clk \
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-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
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# Ignore timing for debug signals to register map
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set_false_path -quiet \
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-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
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@ -1,197 +0,0 @@
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set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
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set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
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# if ... else does not work in xdc files, but expr, well ok...
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set async_src_to_req_clk [expr {$req_clk != $src_clk ? $src_clk : {}}]
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set async_req_to_src_clk [expr {$req_clk != $src_clk ? $req_clk : {}}]
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set async_dest_to_req_clk [expr {$req_clk != $dest_clk ? $dest_clk : {}}]
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set async_req_to_dest_clk [expr {$req_clk != $dest_clk ? $req_clk : {}}]
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set async_dest_to_src_clk [expr {$src_clk != $dest_clk ? $dest_clk : {}}]
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set async_src_to_dest_clk [expr {$src_clk != $dest_clk ? $src_clk : {}}]
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
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[get_cells -quiet -hier *cdc_sync_stage2_reg*]
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#proc get_flops {name inst} {
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# return [get_cells -hier $name \
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# -filter [format {NAME =~ *%s* && PRIMITIVE_SUBGROUP == flop} $name]]
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#}
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#
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#proc set_single_bit_cdc_constraints {name clk} {
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# set_false_path -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}]
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#}
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#
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#proc set_multi_bit_cdc_constraints {name clk} {
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# set_max_delay -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}] \
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# [get_property PERIOD $clk] -datapath_only
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#}
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#
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#proc set_fifo_cdc_constraints {name clk_a clk_b} {
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# set_multi_bit_cdc_constraints ${name}/i_waddr_sync $clk_a
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# set_multi_bit_cdc_constraints ${name}/i_raddr_sync $clk_b
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# set_max_delay -from [get_flops *cdc_sync_fifo_ram_reg* ${name}] -to $clk_b [get_property PERIOD $clk_b] -datapath_only
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#}
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#set_multi_bit_constraints i_sync_src_request_id $req_clk
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#set_multi_bit_constraints i_sync_dest_request_id $src_clk
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#set_multi_bit_constraints i_sync_req_response_id $dest_clk
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set_max_delay -quiet \
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-from $async_req_to_src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_src_to_dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $src_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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#set_single_bit_cdc_constraints i_sync_status_src $src_clk
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#set_single_bit_cdc_constraints i_sync_control_src $req_clk
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#set_single_bit_cdc_constraints i_sync_status_dest $dest_clk
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#set_single_bit_cdc_constraints i_sync_control_dest $req_clk
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set_false_path -quiet \
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-from $async_src_to_req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path -quiet \
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-from $async_req_to_src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}]
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set_false_path -quiet \
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-from $async_req_to_dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}]
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#set_fifo_cdc_constraints i_dest_req_fifo $req_clk $dest_clk
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#set_fifo_cdc_constraints i_dest_response_fifo $dest_clk $req_clk
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#set_fifo_cdc_constraints i_src_req_fifo $req_clk $src_clk
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#set_fifo_cdc_constraints i_src_response_fifo $src_clk $req_clk
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set_max_delay -quiet \
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-from $async_req_to_dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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set_max_delay -quiet \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $async_dest_to_req_clk \
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[get_property PERIOD $dest_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_dest_to_req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $dest_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_req_to_dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay -quiet \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $async_req_to_dest_clk \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_req_to_src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $req_clk] -datapath_only
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set_max_delay -quiet \
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-from $async_src_to_req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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[get_property PERIOD $src_clk] -datapath_only
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set_max_delay -quiet \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
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-to $async_src_to_req_clk \
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[get_property PERIOD $src_clk] -datapath_only
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#set_max_delay \
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# -from $src_clk \
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# -to [get_cells -hier *cdc_sync_stage1_reg* \
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# -filter {NAME =~ *i_src_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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# [get_property PERIOD $src_clk] -datapath_only
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#set_max_delay \
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# -from $req_clk \
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# -to [get_cells -hier *cdc_sync_stage1_reg* \
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# -filter {NAME =~ *i_src_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
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# [get_property PERIOD $req_clk] -datapath_only
|
||||
#set_max_delay \
|
||||
# -from [get_cells -hier *cdc_sync_fifo_ram_reg* \
|
||||
# -filter {NAME =~ *i_src_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
|
||||
# -to $req_clk \
|
||||
# [get_property PERIOD $req_clk] -datapath_only
|
||||
|
||||
#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $src_clk [get_property PERIOD $src_clk] -datapath_only
|
||||
#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $dest_clk [get_property PERIOD $dest_clk] -datapath_only
|
||||
set_max_delay -quiet \
|
||||
-from [get_cells -quiet -hier *eot_mem_reg* \
|
||||
-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
|
||||
-to $async_src_to_req_clk [get_property PERIOD $src_clk] -datapath_only
|
||||
set_max_delay -quiet \
|
||||
-from [get_cells -quiet -hier *eot_mem_reg* \
|
||||
-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
|
||||
-to $async_dest_to_req_clk [get_property PERIOD $dest_clk] -datapath_only
|
||||
|
||||
#set_fifo_cdc_constraints i_fifo $src_clk $dest_clk
|
||||
set_max_delay -quiet \
|
||||
-from $async_src_to_dest_clk \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
|
||||
[get_property PERIOD $src_clk] -datapath_only
|
||||
set_max_delay -quiet \
|
||||
-from $async_dest_to_src_clk \
|
||||
-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
|
||||
-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
|
||||
[get_property PERIOD $dest_clk] -datapath_only
|
||||
|
||||
# Reset signals
|
||||
set_false_path -quiet \
|
||||
-from $req_clk \
|
||||
-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
|
||||
|
||||
# Not sure why, but it seems the built-in constraints for the RAM36B are wrong
|
||||
set_max_delay -quiet \
|
||||
-from $async_dest_to_src_clk \
|
||||
-to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \
|
||||
[get_property PERIOD $dest_clk] -datapath_only
|
||||
|
||||
# Ignore timing for debug signals to register map
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
|
||||
-filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \
|
||||
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
|
||||
-filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \
|
||||
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \
|
||||
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path -quiet \
|
||||
-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \
|
||||
-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
|
||||
|
|
@ -23,10 +23,10 @@ adi_ip_files axi_dmac [list \
|
|||
"splitter.v" \
|
||||
"response_generator.v" \
|
||||
"axi_dmac.v" \
|
||||
"axi_dmac_constr.xdc" ]
|
||||
"axi_dmac_constr.ttcl" ]
|
||||
|
||||
adi_ip_properties axi_dmac
|
||||
adi_ip_constraints axi_dmac "axi_dmac_constr.xdc" "late"
|
||||
adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:util_axis_resize:1.0 \
|
||||
|
|
|
|||
Loading…
Reference in New Issue