diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 8b8c1f3f7..eee93d074 100644 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -46,6 +46,7 @@ module axi_ad9671 ( rx_clk, rx_data, + rx_data_sof, // dma interface @@ -89,6 +90,7 @@ module axi_ad9671 ( input rx_clk; input [(64*PCORE_4L_2L_N)+63:0] rx_data; + input rx_data_sof; // dma interface @@ -181,6 +183,7 @@ module axi_ad9671 ( axi_ad9671_if #(.PCORE_4L_2L_N(PCORE_4L_2L_N)) i_if ( .rx_clk (rx_clk), .rx_data (rx_data), + .rx_data_sof (rx_data_sof), .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_valid (adc_valid_s), diff --git a/library/axi_ad9671/axi_ad9671_if.v b/library/axi_ad9671/axi_ad9671_if.v index b05003a6a..c9373078e 100644 --- a/library/axi_ad9671/axi_ad9671_if.v +++ b/library/axi_ad9671/axi_ad9671_if.v @@ -46,6 +46,7 @@ module axi_ad9671_if ( // rx_clk is (line-rate/40) rx_clk, + rx_data_sof, rx_data, // adc data output @@ -79,6 +80,7 @@ module axi_ad9671_if ( // rx_clk is (line-rate/40) input rx_clk; + input rx_data_sof; input [(64*PCORE_4L_2L_N)+63:0] rx_data; // adc data output @@ -138,8 +140,9 @@ module axi_ad9671_if ( int_valid <= 1'b1; int_data <= rx_data; end else begin - int_valid <= ~int_valid; - int_data <= {rx_data[63:0], int_data[127:64]}; + int_valid <= !rx_data_sof; + int_data[63:0] <= {rx_data[31:0], int_data[63:32]}; + int_data[127:64] <= {rx_data[63:32], int_data[127:96]}; end end diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index 583eb5284..fb2ee3a30 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -62,6 +62,7 @@ module axi_jesd_gt ( rx_clk_g, rx_clk, rx_data, + rx_data_sof, rx_gt_charisk, rx_gt_disperr, rx_gt_notintable, @@ -71,7 +72,7 @@ module axi_jesd_gt ( rx_ip_sync, rx_ip_sof, rx_ip_data, - + tx_rst, tx_clk_g, tx_clk, @@ -185,6 +186,7 @@ module axi_jesd_gt ( output rx_clk_g; input rx_clk; output [((PCORE_NUM_OF_LANES*32)-1):0] rx_data; + output [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_sof; output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_charisk; output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr; output [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable; @@ -499,6 +501,7 @@ module axi_jesd_gt ( .rx_clk (rx_clk), .rx_sof (rx_ip_sof), .rx_ip_data (rx_ip_data[n*32+31:n*32]), + .rx_data_sof(rx_data_sof[n]), .rx_data (rx_data[n*32+31:n*32])); ad_gt_channel_1 #( diff --git a/library/common/ad_jesd_align.v b/library/common/ad_jesd_align.v index 2d571923e..b9f0f9b30 100644 --- a/library/common/ad_jesd_align.v +++ b/library/common/ad_jesd_align.v @@ -44,6 +44,7 @@ module ad_jesd_align ( rx_clk, rx_sof, rx_ip_data, + rx_data_sof, rx_data); // jesd interface @@ -54,6 +55,7 @@ module ad_jesd_align ( // aligned data + output rx_data_sof; output [31:0] rx_data; // internal registers @@ -64,8 +66,10 @@ module ad_jesd_align ( // dword may contain more than one frame per clock + assign rx_data_sof = |rx_sof; + always @(posedge rx_clk) begin - rx_ip_data_d <= rx_ip_data; + rx_ip_data_d <= rx_ip_data; if (rx_sof != 4'h0) begin rx_sof_d <= rx_sof; diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index ad8654d77..37e48ca5c 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -15,30 +15,35 @@ set rx_sysref [create_bd_port -dir O rx_sysref] set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] -set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data] -set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0] -set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1] -set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2] -set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3] -set adc_data_0 [create_bd_port -dir O -from 127 -to 0 adc_data_0] -set adc_data_1 [create_bd_port -dir O -from 127 -to 0 adc_data_1] -set adc_data_2 [create_bd_port -dir O -from 127 -to 0 adc_data_2] -set adc_data_3 [create_bd_port -dir O -from 127 -to 0 adc_data_3] -set adc_valid_0 [create_bd_port -dir O -from 7 -to 0 adc_valid_0] -set adc_valid_1 [create_bd_port -dir O -from 7 -to 0 adc_valid_1] -set adc_valid_2 [create_bd_port -dir O -from 7 -to 0 adc_valid_2] -set adc_valid_3 [create_bd_port -dir O -from 7 -to 0 adc_valid_3] -set adc_enable_0 [create_bd_port -dir O -from 7 -to 0 adc_enable_0] -set adc_enable_1 [create_bd_port -dir O -from 7 -to 0 adc_enable_1] -set adc_enable_2 [create_bd_port -dir O -from 7 -to 0 adc_enable_2] -set adc_enable_3 [create_bd_port -dir O -from 7 -to 0 adc_enable_3] -set adc_dovf_0 [create_bd_port -dir I adc_dovf_0] -set adc_dovf_1 [create_bd_port -dir I adc_dovf_1] -set adc_dovf_2 [create_bd_port -dir I adc_dovf_2] -set adc_dovf_3 [create_bd_port -dir I adc_dovf_3] -set adc_data [create_bd_port -dir I -from 511 -to 0 adc_data] -set adc_wr_en [create_bd_port -dir I adc_wr_en] -set adc_dovf [create_bd_port -dir O adc_dovf] +set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data] +set gt_rx_data_sof [create_bd_port -dir O -from 3 -to 0 gt_rx_data_sof] +set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0] +set gt_rx_data_sof_0 [create_bd_port -dir I gt_rx_data_sof_0] +set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1] +set gt_rx_data_sof_1 [create_bd_port -dir I gt_rx_data_sof_1] +set gt_rx_data_2 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_2] +set gt_rx_data_sof_2 [create_bd_port -dir I gt_rx_data_sof_2] +set gt_rx_data_3 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_3] +set gt_rx_data_sof_3 [create_bd_port -dir I gt_rx_data_sof_3] +set adc_data_0 [create_bd_port -dir O -from 127 -to 0 adc_data_0] +set adc_data_1 [create_bd_port -dir O -from 127 -to 0 adc_data_1] +set adc_data_2 [create_bd_port -dir O -from 127 -to 0 adc_data_2] +set adc_data_3 [create_bd_port -dir O -from 127 -to 0 adc_data_3] +set adc_valid_0 [create_bd_port -dir O -from 7 -to 0 adc_valid_0] +set adc_valid_1 [create_bd_port -dir O -from 7 -to 0 adc_valid_1] +set adc_valid_2 [create_bd_port -dir O -from 7 -to 0 adc_valid_2] +set adc_valid_3 [create_bd_port -dir O -from 7 -to 0 adc_valid_3] +set adc_enable_0 [create_bd_port -dir O -from 7 -to 0 adc_enable_0] +set adc_enable_1 [create_bd_port -dir O -from 7 -to 0 adc_enable_1] +set adc_enable_2 [create_bd_port -dir O -from 7 -to 0 adc_enable_2] +set adc_enable_3 [create_bd_port -dir O -from 7 -to 0 adc_enable_3] +set adc_dovf_0 [create_bd_port -dir I adc_dovf_0] +set adc_dovf_1 [create_bd_port -dir I adc_dovf_1] +set adc_dovf_2 [create_bd_port -dir I adc_dovf_2] +set adc_dovf_3 [create_bd_port -dir I adc_dovf_3] +set adc_data [create_bd_port -dir I -from 511 -to 0 adc_data] +set adc_wr_en [create_bd_port -dir I adc_wr_en] +set adc_dovf [create_bd_port -dir O adc_dovf] # adc peripherals @@ -108,9 +113,9 @@ set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {59}] $sys_ps7 -set_property LEFT 43 [get_bd_ports GPIO_I] -set_property LEFT 43 [get_bd_ports GPIO_O] -set_property LEFT 43 [get_bd_ports GPIO_T] +set_property LEFT 58 [get_bd_ports GPIO_I] +set_property LEFT 58 [get_bd_ports GPIO_O] +set_property LEFT 58 [get_bd_ports GPIO_T] # connections (spi and gpio) @@ -155,10 +160,15 @@ connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/r connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame] connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata] connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data] [get_bd_ports gt_rx_data] +connect_bd_net -net axi_usdrx1_gt_rx_data_sof [get_bd_pins axi_usdrx1_gt/rx_data_sof] [get_bd_ports gt_rx_data_sof] connect_bd_net -net axi_usdrx1_gt_rx_data_0 [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_ports gt_rx_data_0] +connect_bd_net -net axi_usdrx1_gt_rx_data_sof_0 [get_bd_pins axi_ad9671_core_0/rx_data_sof] [get_bd_ports gt_rx_data_sof_0] connect_bd_net -net axi_usdrx1_gt_rx_data_1 [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_ports gt_rx_data_1] +connect_bd_net -net axi_usdrx1_gt_rx_data_sof_1 [get_bd_pins axi_ad9671_core_1/rx_data_sof] [get_bd_ports gt_rx_data_sof_1] connect_bd_net -net axi_usdrx1_gt_rx_data_2 [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_ports gt_rx_data_2] +connect_bd_net -net axi_usdrx1_gt_rx_data_sof_2 [get_bd_pins axi_ad9671_core_2/rx_data_sof] [get_bd_ports gt_rx_data_sof_2] connect_bd_net -net axi_usdrx1_gt_rx_data_3 [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_ports gt_rx_data_3] +connect_bd_net -net axi_usdrx1_gt_rx_data_sof_3 [get_bd_pins axi_ad9671_core_3/rx_data_sof] [get_bd_ports gt_rx_data_sof_3] connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk] connect_bd_net -net axi_ad9671_core_adc_data_0 [get_bd_pins axi_ad9671_core_0/adc_data] [get_bd_ports adc_data_0] connect_bd_net -net axi_ad9671_core_adc_data_1 [get_bd_pins axi_ad9671_core_1/adc_data] [get_bd_ports adc_data_1] diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index 758798222..84a2dea72 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -226,10 +226,15 @@ module system_top ( wire adc_dovf_2; wire adc_dovf_3; wire [255:0] gt_rx_data; + wire [7:0] gt_rx_data_sof; wire [63:0] gt_rx_data_0; + wire gt_rx_data_sof_0; wire [63:0] gt_rx_data_1; + wire gt_rx_data_sof_1; wire [63:0] gt_rx_data_2; + wire gt_rx_data_sof_2; wire [63:0] gt_rx_data_3; + wire gt_rx_data_sof_3; wire [58:0] gpio_i; wire [58:0] gpio_o; wire [58:0] gpio_t; @@ -264,6 +269,10 @@ module system_top ( assign gt_rx_data_2 = gt_rx_data[191:128]; assign gt_rx_data_1 = gt_rx_data[127: 64]; assign gt_rx_data_0 = gt_rx_data[ 63: 0]; + assign gt_rx_data_sof_0 = gt_rx_data_sof [0] | gt_rx_data_sof [1]; + assign gt_rx_data_sof_1 = gt_rx_data_sof [2] | gt_rx_data_sof [3]; + assign gt_rx_data_sof_2 = gt_rx_data_sof [4] | gt_rx_data_sof [5]; + assign gt_rx_data_sof_3 = gt_rx_data_sof [6] | gt_rx_data_sof [7]; assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0}; assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ; @@ -394,10 +403,15 @@ module system_top ( .adc_dovf_2 (adc_dovf_2), .adc_dovf_3 (adc_dovf_3), .gt_rx_data (gt_rx_data), + .gt_rx_data_sof (gt_rx_data_sof), .gt_rx_data_0 (gt_rx_data_0), + .gt_rx_data_sof_0(gt_rx_data_sof_0), .gt_rx_data_1 (gt_rx_data_1), + .gt_rx_data_sof_1(gt_rx_data_sof_1), .gt_rx_data_2 (gt_rx_data_2), + .gt_rx_data_sof_2(gt_rx_data_sof_2), .gt_rx_data_3 (gt_rx_data_3), + .gt_rx_data_sof_3(gt_rx_data_sof_3), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync),