projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.
dbogdan
parent
c435edf194
commit
5a42c10233
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@ -20,59 +20,59 @@ set_location_assignment PIN_AH3 -to vga_blank_n
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set_location_assignment PIN_AG2 -to vga_sync_n
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set_location_assignment PIN_AD12 -to vga_hs
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set_location_assignment PIN_AC12 -to vga_vs
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set_location_assignment PIN_AE28 -to vga_data[0]
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set_location_assignment PIN_Y23 -to vga_data[1]
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set_location_assignment PIN_Y24 -to vga_data[2]
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set_location_assignment PIN_AG28 -to vga_data[3]
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set_location_assignment PIN_AF28 -to vga_data[4]
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set_location_assignment PIN_V23 -to vga_data[5]
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set_location_assignment PIN_W24 -to vga_data[6]
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set_location_assignment PIN_AF29 -to vga_data[7]
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set_location_assignment PIN_Y21 -to vga_data[8]
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set_location_assignment PIN_AA25 -to vga_data[9]
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set_location_assignment PIN_AB26 -to vga_data[10]
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set_location_assignment PIN_AB22 -to vga_data[11]
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set_location_assignment PIN_AB23 -to vga_data[12]
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set_location_assignment PIN_AA24 -to vga_data[13]
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set_location_assignment PIN_AB25 -to vga_data[14]
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set_location_assignment PIN_AE27 -to vga_data[15]
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set_location_assignment PIN_AA12 -to vga_data[16]
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set_location_assignment PIN_AB12 -to vga_data[17]
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set_location_assignment PIN_AF6 -to vga_data[18]
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set_location_assignment PIN_AG6 -to vga_data[19]
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set_location_assignment PIN_AG5 -to vga_data[20]
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set_location_assignment PIN_AH5 -to vga_data[21]
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set_location_assignment PIN_AJ1 -to vga_data[22]
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set_location_assignment PIN_AJ2 -to vga_data[23]
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set_location_assignment PIN_AF29 -to vga_b[7]
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set_location_assignment PIN_AE28 -to vga_b[0]
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set_location_assignment PIN_Y23 -to vga_b[1]
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set_location_assignment PIN_Y24 -to vga_b[2]
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set_location_assignment PIN_AG28 -to vga_b[3]
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set_location_assignment PIN_AF28 -to vga_b[4]
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set_location_assignment PIN_V23 -to vga_b[5]
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set_location_assignment PIN_W24 -to vga_b[6]
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set_location_assignment PIN_Y21 -to vga_g[0]
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set_location_assignment PIN_AA25 -to vga_g[1]
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set_location_assignment PIN_AB26 -to vga_g[2]
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set_location_assignment PIN_AB22 -to vga_g[3]
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set_location_assignment PIN_AB23 -to vga_g[4]
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set_location_assignment PIN_AA24 -to vga_g[5]
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set_location_assignment PIN_AB25 -to vga_g[6]
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set_location_assignment PIN_AE27 -to vga_g[7]
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set_location_assignment PIN_AG5 -to vga_r[0]
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set_location_assignment PIN_AA12 -to vga_r[1]
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set_location_assignment PIN_AB12 -to vga_r[2]
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set_location_assignment PIN_AF6 -to vga_r[3]
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set_location_assignment PIN_AG6 -to vga_r[4]
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set_location_assignment PIN_AJ2 -to vga_r[5]
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set_location_assignment PIN_AH5 -to vga_r[6]
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set_location_assignment PIN_AJ1 -to vga_r[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_clk
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_blank_n
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_sync_n
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_hs
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_vs
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[8]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[9]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[10]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[11]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[12]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[13]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[14]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[15]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[16]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[17]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[18]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[19]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[20]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[21]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[22]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_data[23]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_g[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_r[7]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[0]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[1]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[2]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[3]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[4]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[5]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[6]
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to vga_b[7]
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# led & switches
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@ -12,6 +12,22 @@
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element $${FILENAME}
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{
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}
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element adc_pack
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{
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datum _sortIndex
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{
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value = "7";
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type = "int";
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}
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}
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element vga_frame_reader.avalon_slave
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{
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datum baseAddress
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{
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value = "36864";
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type = "String";
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}
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}
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element axi_ad9361
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{
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datum _sortIndex
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@ -24,7 +40,7 @@
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{
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datum _sortIndex
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{
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value = "7";
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value = "8";
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type = "int";
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}
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}
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@ -86,6 +102,14 @@
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type = "String";
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}
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}
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element axi_dmac_adc.s_axi
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{
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datum baseAddress
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{
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value = "0";
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type = "String";
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}
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}
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element axi_dmac_dac.s_axi
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{
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datum baseAddress
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@ -102,11 +126,19 @@
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type = "String";
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}
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}
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element axi_dmac_adc.s_axi
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element spi_ad9361
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{
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datum _sortIndex
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{
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value = "9";
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type = "int";
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}
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}
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element spi_ad9361.spi_control_port
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{
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datum baseAddress
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{
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value = "0";
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value = "32768";
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type = "String";
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}
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}
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@ -150,6 +182,38 @@
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type = "int";
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}
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}
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element vga_clock_video_output
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{
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datum _sortIndex
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{
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value = "13";
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type = "int";
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}
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}
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element vga_frame_reader
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{
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datum _sortIndex
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{
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value = "12";
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type = "int";
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}
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}
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element vga_pixel_clock_bridge
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{
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datum _sortIndex
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{
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value = "11";
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type = "int";
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}
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}
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element vga_pll
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{
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datum _sortIndex
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{
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value = "10";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="FIFO" />
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@ -260,6 +324,31 @@
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internal="axi_dmac_adc.fifo_wr_if"
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type="conduit"
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dir="end" />
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<interface
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name="spi_ad9361_external"
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internal="spi_ad9361.external"
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type="conduit"
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dir="end" />
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<interface
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name="vga_pixel_clock_bridge_out_clk"
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internal="vga_pixel_clock_bridge.out_clk"
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type="clock"
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dir="start" />
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<interface
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name="vga_clock_video_output_clocked_video"
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internal="vga_clock_video_output.clocked_video"
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type="conduit"
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dir="end" />
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<interface
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name="adc_pack_data_clock"
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internal="adc_pack.data_clock"
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type="clock"
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dir="end" />
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<interface
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name="adc_pack_channels_data"
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internal="adc_pack.channels_data"
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type="conduit"
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dir="end" />
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<module kind="clock_source" version="14.0" enabled="1" name="sys_clk">
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<parameter name="clockFrequency" value="50000000" />
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<parameter name="clockFrequencyKnown" value="true" />
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@ -652,10 +741,10 @@
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<parameter name="BSEL" value="1" />
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<parameter name="CSEL_EN" value="false" />
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<parameter name="CSEL" value="0" />
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<parameter name="F2S_Width" value="0" />
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<parameter name="F2S_Width" value="2" />
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<parameter name="S2F_Width" value="2" />
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<parameter name="LWH2F_Enable" value="true" />
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<parameter name="F2SDRAM_Type" value="AXI-3" />
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<parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter>
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<parameter name="F2SDRAM_Width" value="64" />
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<parameter name="BONDING_OUT_ENABLED" value="false" />
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<parameter name="S2FCLK_COLDRST_Enable" value="false" />
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@ -726,7 +815,7 @@
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<parameter name="TRACE_Mode" value="N/A" />
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<parameter name="GPIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
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<parameter name="LOANIO_Enable">No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No</parameter>
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<parameter name="F2H_AXI_CLOCK_FREQ" value="100" />
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<parameter name="F2H_AXI_CLOCK_FREQ" value="50000000" />
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<parameter name="H2F_AXI_CLOCK_FREQ" value="50000000" />
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<parameter name="H2F_LW_AXI_CLOCK_FREQ" value="50000000" />
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<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="80000000" />
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@ -880,6 +969,296 @@
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<parameter name="C_DMA_TYPE_SRC" value="2" />
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<parameter name="AUTO_S_AXI_CLOCK_CLOCK_RATE" value="50000000" />
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</module>
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<module kind="altera_avalon_spi" version="14.0" enabled="1" name="spi_ad9361">
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<parameter name="clockPhase" value="0" />
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<parameter name="clockPolarity" value="1" />
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<parameter name="dataWidth" value="8" />
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<parameter name="disableAvalonFlowControl" value="false" />
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<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
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<parameter name="insertSync" value="false" />
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<parameter name="lsbOrderedFirst" value="false" />
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<parameter name="masterSPI" value="true" />
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<parameter name="numberOfSlaves" value="1" />
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<parameter name="syncRegDepth" value="2" />
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<parameter name="targetClockRate" value="1000000" />
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<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
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<parameter name="avalonSpec" value="2.0" />
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<parameter name="inputClockRate" value="50000000" />
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</module>
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<module kind="altera_pll" version="14.0" enabled="1" name="vga_pll">
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<parameter name="debug_print_output" value="false" />
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<parameter name="debug_use_rbc_taf_method" value="false" />
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<parameter name="device_family" value="Cyclone V" />
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<parameter name="device" value="5CSXFC6D6F31C8ES" />
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<parameter name="gui_device_speed_grade" value="1" />
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<parameter name="gui_pll_mode" value="Integer-N PLL" />
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<parameter name="gui_reference_clock_frequency" value="50.0" />
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<parameter name="gui_channel_spacing" value="0.0" />
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<parameter name="gui_operation_mode" value="direct" />
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<parameter name="gui_feedback_clock" value="Global Clock" />
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<parameter name="gui_fractional_cout" value="32" />
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<parameter name="gui_dsm_out_sel" value="1st_order" />
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<parameter name="gui_use_locked" value="false" />
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<parameter name="gui_en_adv_params" value="false" />
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<parameter name="gui_number_of_clocks" value="2" />
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<parameter name="gui_multiply_factor" value="1" />
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<parameter name="gui_frac_multiply_factor" value="1" />
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<parameter name="gui_divide_factor_n" value="1" />
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<parameter name="gui_cascade_counter0" value="false" />
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<parameter name="gui_output_clock_frequency0" value="85.5" />
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<parameter name="gui_divide_factor_c0" value="1" />
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<parameter name="gui_actual_output_clock_frequency0" value="0 MHz" />
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<parameter name="gui_ps_units0" value="ps" />
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<parameter name="gui_phase_shift0" value="0" />
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<parameter name="gui_phase_shift_deg0" value="0.0" />
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<parameter name="gui_actual_phase_shift0" value="0" />
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<parameter name="gui_duty_cycle0" value="50" />
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<parameter name="gui_cascade_counter1" value="false" />
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<parameter name="gui_output_clock_frequency1" value="171.0" />
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<parameter name="gui_divide_factor_c1" value="1" />
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<parameter name="gui_actual_output_clock_frequency1" value="0 MHz" />
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<parameter name="gui_ps_units1" value="ps" />
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<parameter name="gui_phase_shift1" value="0" />
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<parameter name="gui_phase_shift_deg1" value="0.0" />
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<parameter name="gui_actual_phase_shift1" value="0" />
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<parameter name="gui_duty_cycle1" value="50" />
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<parameter name="gui_cascade_counter2" value="false" />
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<parameter name="gui_output_clock_frequency2" value="100.0" />
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<parameter name="gui_divide_factor_c2" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency2" value="0 MHz" />
|
||||
<parameter name="gui_ps_units2" value="ps" />
|
||||
<parameter name="gui_phase_shift2" value="0" />
|
||||
<parameter name="gui_phase_shift_deg2" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift2" value="0" />
|
||||
<parameter name="gui_duty_cycle2" value="50" />
|
||||
<parameter name="gui_cascade_counter3" value="false" />
|
||||
<parameter name="gui_output_clock_frequency3" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c3" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency3" value="0 MHz" />
|
||||
<parameter name="gui_ps_units3" value="ps" />
|
||||
<parameter name="gui_phase_shift3" value="0" />
|
||||
<parameter name="gui_phase_shift_deg3" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift3" value="0" />
|
||||
<parameter name="gui_duty_cycle3" value="50" />
|
||||
<parameter name="gui_cascade_counter4" value="false" />
|
||||
<parameter name="gui_output_clock_frequency4" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c4" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency4" value="0 MHz" />
|
||||
<parameter name="gui_ps_units4" value="ps" />
|
||||
<parameter name="gui_phase_shift4" value="0" />
|
||||
<parameter name="gui_phase_shift_deg4" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift4" value="0" />
|
||||
<parameter name="gui_duty_cycle4" value="50" />
|
||||
<parameter name="gui_cascade_counter5" value="false" />
|
||||
<parameter name="gui_output_clock_frequency5" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c5" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency5" value="0 MHz" />
|
||||
<parameter name="gui_ps_units5" value="ps" />
|
||||
<parameter name="gui_phase_shift5" value="0" />
|
||||
<parameter name="gui_phase_shift_deg5" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift5" value="0" />
|
||||
<parameter name="gui_duty_cycle5" value="50" />
|
||||
<parameter name="gui_cascade_counter6" value="false" />
|
||||
<parameter name="gui_output_clock_frequency6" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c6" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency6" value="0 MHz" />
|
||||
<parameter name="gui_ps_units6" value="ps" />
|
||||
<parameter name="gui_phase_shift6" value="0" />
|
||||
<parameter name="gui_phase_shift_deg6" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift6" value="0" />
|
||||
<parameter name="gui_duty_cycle6" value="50" />
|
||||
<parameter name="gui_cascade_counter7" value="false" />
|
||||
<parameter name="gui_output_clock_frequency7" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c7" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency7" value="0 MHz" />
|
||||
<parameter name="gui_ps_units7" value="ps" />
|
||||
<parameter name="gui_phase_shift7" value="0" />
|
||||
<parameter name="gui_phase_shift_deg7" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift7" value="0" />
|
||||
<parameter name="gui_duty_cycle7" value="50" />
|
||||
<parameter name="gui_cascade_counter8" value="false" />
|
||||
<parameter name="gui_output_clock_frequency8" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c8" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency8" value="0 MHz" />
|
||||
<parameter name="gui_ps_units8" value="ps" />
|
||||
<parameter name="gui_phase_shift8" value="0" />
|
||||
<parameter name="gui_phase_shift_deg8" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift8" value="0" />
|
||||
<parameter name="gui_duty_cycle8" value="50" />
|
||||
<parameter name="gui_cascade_counter9" value="false" />
|
||||
<parameter name="gui_output_clock_frequency9" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c9" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency9" value="0 MHz" />
|
||||
<parameter name="gui_ps_units9" value="ps" />
|
||||
<parameter name="gui_phase_shift9" value="0" />
|
||||
<parameter name="gui_phase_shift_deg9" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift9" value="0" />
|
||||
<parameter name="gui_duty_cycle9" value="50" />
|
||||
<parameter name="gui_cascade_counter10" value="false" />
|
||||
<parameter name="gui_output_clock_frequency10" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c10" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency10" value="0 MHz" />
|
||||
<parameter name="gui_ps_units10" value="ps" />
|
||||
<parameter name="gui_phase_shift10" value="0" />
|
||||
<parameter name="gui_phase_shift_deg10" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift10" value="0" />
|
||||
<parameter name="gui_duty_cycle10" value="50" />
|
||||
<parameter name="gui_cascade_counter11" value="false" />
|
||||
<parameter name="gui_output_clock_frequency11" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c11" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency11" value="0 MHz" />
|
||||
<parameter name="gui_ps_units11" value="ps" />
|
||||
<parameter name="gui_phase_shift11" value="0" />
|
||||
<parameter name="gui_phase_shift_deg11" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift11" value="0" />
|
||||
<parameter name="gui_duty_cycle11" value="50" />
|
||||
<parameter name="gui_cascade_counter12" value="false" />
|
||||
<parameter name="gui_output_clock_frequency12" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c12" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency12" value="0 MHz" />
|
||||
<parameter name="gui_ps_units12" value="ps" />
|
||||
<parameter name="gui_phase_shift12" value="0" />
|
||||
<parameter name="gui_phase_shift_deg12" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift12" value="0" />
|
||||
<parameter name="gui_duty_cycle12" value="50" />
|
||||
<parameter name="gui_cascade_counter13" value="false" />
|
||||
<parameter name="gui_output_clock_frequency13" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c13" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency13" value="0 MHz" />
|
||||
<parameter name="gui_ps_units13" value="ps" />
|
||||
<parameter name="gui_phase_shift13" value="0" />
|
||||
<parameter name="gui_phase_shift_deg13" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift13" value="0" />
|
||||
<parameter name="gui_duty_cycle13" value="50" />
|
||||
<parameter name="gui_cascade_counter14" value="false" />
|
||||
<parameter name="gui_output_clock_frequency14" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c14" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency14" value="0 MHz" />
|
||||
<parameter name="gui_ps_units14" value="ps" />
|
||||
<parameter name="gui_phase_shift14" value="0" />
|
||||
<parameter name="gui_phase_shift_deg14" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift14" value="0" />
|
||||
<parameter name="gui_duty_cycle14" value="50" />
|
||||
<parameter name="gui_cascade_counter15" value="false" />
|
||||
<parameter name="gui_output_clock_frequency15" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c15" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency15" value="0 MHz" />
|
||||
<parameter name="gui_ps_units15" value="ps" />
|
||||
<parameter name="gui_phase_shift15" value="0" />
|
||||
<parameter name="gui_phase_shift_deg15" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift15" value="0" />
|
||||
<parameter name="gui_duty_cycle15" value="50" />
|
||||
<parameter name="gui_cascade_counter16" value="false" />
|
||||
<parameter name="gui_output_clock_frequency16" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c16" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency16" value="0 MHz" />
|
||||
<parameter name="gui_ps_units16" value="ps" />
|
||||
<parameter name="gui_phase_shift16" value="0" />
|
||||
<parameter name="gui_phase_shift_deg16" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift16" value="0" />
|
||||
<parameter name="gui_duty_cycle16" value="50" />
|
||||
<parameter name="gui_cascade_counter17" value="false" />
|
||||
<parameter name="gui_output_clock_frequency17" value="100.0" />
|
||||
<parameter name="gui_divide_factor_c17" value="1" />
|
||||
<parameter name="gui_actual_output_clock_frequency17" value="0 MHz" />
|
||||
<parameter name="gui_ps_units17" value="ps" />
|
||||
<parameter name="gui_phase_shift17" value="0" />
|
||||
<parameter name="gui_phase_shift_deg17" value="0.0" />
|
||||
<parameter name="gui_actual_phase_shift17" value="0" />
|
||||
<parameter name="gui_duty_cycle17" value="50" />
|
||||
<parameter name="gui_pll_auto_reset" value="Off" />
|
||||
<parameter name="gui_pll_bandwidth_preset" value="Auto" />
|
||||
<parameter name="gui_en_reconf" value="false" />
|
||||
<parameter name="gui_en_dps_ports" value="false" />
|
||||
<parameter name="gui_en_phout_ports" value="false" />
|
||||
<parameter name="gui_phout_division" value="1" />
|
||||
<parameter name="gui_en_lvds_ports" value="false" />
|
||||
<parameter name="gui_mif_generate" value="false" />
|
||||
<parameter name="gui_enable_mif_dps" value="false" />
|
||||
<parameter name="gui_dps_cntr" value="C0" />
|
||||
<parameter name="gui_dps_num" value="1" />
|
||||
<parameter name="gui_dps_dir" value="Positive" />
|
||||
<parameter name="gui_refclk_switch" value="false" />
|
||||
<parameter name="gui_refclk1_frequency" value="100.0" />
|
||||
<parameter name="gui_switchover_mode">Automatic Switchover</parameter>
|
||||
<parameter name="gui_switchover_delay" value="0" />
|
||||
<parameter name="gui_active_clk" value="false" />
|
||||
<parameter name="gui_clk_bad" value="false" />
|
||||
<parameter name="gui_enable_cascade_out" value="false" />
|
||||
<parameter name="gui_cascade_outclk_index" value="0" />
|
||||
<parameter name="gui_enable_cascade_in" value="false" />
|
||||
<parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter>
|
||||
<parameter name="AUTO_REFCLK_CLOCK_RATE" value="50000000" />
|
||||
</module>
|
||||
<module
|
||||
kind="altera_clock_bridge"
|
||||
version="14.0"
|
||||
enabled="1"
|
||||
name="vga_pixel_clock_bridge">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="85500000" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module kind="alt_vip_vfr" version="14.0" enabled="1" name="vga_frame_reader">
|
||||
<parameter name="FAMILY" value="Cyclone V" />
|
||||
<parameter name="BITS_PER_PIXEL_PER_COLOR_PLANE" value="8" />
|
||||
<parameter name="NUMBER_OF_CHANNELS_IN_PARALLEL" value="4" />
|
||||
<parameter name="NUMBER_OF_CHANNELS_IN_SEQUENCE" value="1" />
|
||||
<parameter name="MAX_IMAGE_WIDTH" value="1360" />
|
||||
<parameter name="MAX_IMAGE_HEIGHT" value="768" />
|
||||
<parameter name="MEM_PORT_WIDTH" value="128" />
|
||||
<parameter name="RMASTER_FIFO_DEPTH" value="64" />
|
||||
<parameter name="RMASTER_BURST_TARGET" value="32" />
|
||||
<parameter name="CLOCKS_ARE_SEPARATE" value="1" />
|
||||
<parameter name="AUTO_CLOCK_RESET_CLOCK_RATE" value="85500000" />
|
||||
<parameter name="AUTO_CLOCK_MASTER_CLOCK_RATE" value="50000000" />
|
||||
</module>
|
||||
<module
|
||||
kind="alt_vip_itc"
|
||||
version="14.0"
|
||||
enabled="1"
|
||||
name="vga_clock_video_output">
|
||||
<parameter name="FAMILY" value="Cyclone V" />
|
||||
<parameter name="NUMBER_OF_COLOUR_PLANES" value="4" />
|
||||
<parameter name="COLOUR_PLANES_ARE_IN_PARALLEL" value="1" />
|
||||
<parameter name="BPS" value="8" />
|
||||
<parameter name="INTERLACED" value="0" />
|
||||
<parameter name="H_ACTIVE_PIXELS" value="1360" />
|
||||
<parameter name="V_ACTIVE_LINES" value="768" />
|
||||
<parameter name="ACCEPT_COLOURS_IN_SEQ" value="0" />
|
||||
<parameter name="FIFO_DEPTH" value="1920" />
|
||||
<parameter name="CLOCKS_ARE_SAME" value="0" />
|
||||
<parameter name="USE_CONTROL" value="0" />
|
||||
<parameter name="NO_OF_MODES" value="1" />
|
||||
<parameter name="THRESHOLD" value="1919" />
|
||||
<parameter name="STD_WIDTH" value="1" />
|
||||
<parameter name="GENERATE_SYNC" value="0" />
|
||||
<parameter name="USE_EMBEDDED_SYNCS" value="0" />
|
||||
<parameter name="AP_LINE" value="0" />
|
||||
<parameter name="V_BLANK" value="0" />
|
||||
<parameter name="H_BLANK" value="0" />
|
||||
<parameter name="H_SYNC_LENGTH" value="112" />
|
||||
<parameter name="H_FRONT_PORCH" value="64" />
|
||||
<parameter name="H_BACK_PORCH" value="256" />
|
||||
<parameter name="V_SYNC_LENGTH" value="6" />
|
||||
<parameter name="V_FRONT_PORCH" value="3" />
|
||||
<parameter name="V_BACK_PORCH" value="18" />
|
||||
<parameter name="F_RISING_EDGE" value="0" />
|
||||
<parameter name="F_FALLING_EDGE" value="0" />
|
||||
<parameter name="FIELD0_V_RISING_EDGE" value="0" />
|
||||
<parameter name="FIELD0_V_BLANK" value="0" />
|
||||
<parameter name="FIELD0_V_SYNC_LENGTH" value="0" />
|
||||
<parameter name="FIELD0_V_FRONT_PORCH" value="0" />
|
||||
<parameter name="FIELD0_V_BACK_PORCH" value="0" />
|
||||
<parameter name="ANC_LINE" value="0" />
|
||||
<parameter name="FIELD0_ANC_LINE" value="0" />
|
||||
<parameter name="AUTO_IS_CLK_RST_CLOCK_RATE" value="85500000" />
|
||||
</module>
|
||||
<module kind="util_adc_pack" version="1.0" enabled="1" name="adc_pack">
|
||||
<parameter name="CHANNELS" value="4" />
|
||||
<parameter name="DATA_WIDTH" value="16" />
|
||||
<parameter name="AUTO_DATA_CLOCK_CLOCK_RATE" value="0" />
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="14.0"
|
||||
|
|
@ -1065,6 +1444,104 @@
|
|||
end="axi_dmac_adc.interrupt_sender">
|
||||
<parameter name="irqNumber" value="2" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="14.0"
|
||||
start="sys_hps.f2h_irq0"
|
||||
end="spi_ad9361.irq">
|
||||
<parameter name="irqNumber" value="3" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="14.0"
|
||||
start="sys_hps.h2f_lw_axi_master"
|
||||
end="spi_ad9361.spi_control_port">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x8000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="14.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="spi_ad9361.reset" />
|
||||
<connection kind="clock" version="14.0" start="sys_clk.clk" end="spi_ad9361.clk" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="14.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="vga_pll.reset" />
|
||||
<connection kind="clock" version="14.0" start="sys_clk.clk" end="vga_pll.refclk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="14.0"
|
||||
start="vga_pll.outclk0"
|
||||
end="vga_pixel_clock_bridge.in_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="14.0"
|
||||
start="vga_pll.outclk0"
|
||||
end="vga_frame_reader.clock_reset" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="14.0"
|
||||
start="vga_pll.outclk0"
|
||||
end="vga_clock_video_output.is_clk_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="14.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="vga_clock_video_output.is_clk_rst_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="14.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="vga_frame_reader.clock_reset_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="14.0"
|
||||
start="sys_clk.clk_reset"
|
||||
end="vga_frame_reader.clock_master_reset" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="14.0"
|
||||
start="sys_clk.clk"
|
||||
end="vga_frame_reader.clock_master" />
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="14.0"
|
||||
start="sys_hps.h2f_lw_axi_master"
|
||||
end="vga_frame_reader.avalon_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x9000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon_streaming"
|
||||
version="14.0"
|
||||
start="vga_frame_reader.avalon_streaming_source"
|
||||
end="vga_clock_video_output.din" />
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="14.0"
|
||||
start="vga_frame_reader.avalon_master"
|
||||
end="sys_hps.f2h_axi_slave">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="14.0"
|
||||
start="sys_clk.clk"
|
||||
end="sys_hps.f2h_axi_clock" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="14.0"
|
||||
start="sys_hps.f2h_irq0"
|
||||
end="vga_frame_reader.interrupt_sender">
|
||||
<parameter name="irqNumber" value="4" />
|
||||
</connection>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
</system>
|
||||
|
|
|
|||
|
|
@ -119,7 +119,9 @@ module system_top (
|
|||
vga_sync_n,
|
||||
vga_hs,
|
||||
vga_vs,
|
||||
vga_data,
|
||||
vga_r,
|
||||
vga_g,
|
||||
vga_b,
|
||||
|
||||
// data interface
|
||||
|
||||
|
|
@ -221,7 +223,9 @@ module system_top (
|
|||
output vga_sync_n;
|
||||
output vga_hs;
|
||||
output vga_vs;
|
||||
output [ 23:0] vga_data;
|
||||
output [ 7:0] vga_r;
|
||||
output [ 7:0] vga_g;
|
||||
output [ 7:0] vga_b;
|
||||
|
||||
// data interface
|
||||
|
||||
|
|
@ -251,9 +255,20 @@ module system_top (
|
|||
|
||||
// internal signals
|
||||
|
||||
wire adc_enable;
|
||||
wire adc_valid;
|
||||
wire adc_enable_i0;
|
||||
wire adc_enable_q0;
|
||||
wire adc_enable_i1;
|
||||
wire adc_enable_q2;
|
||||
wire adc_valid_i0;
|
||||
wire adc_valid_q0;
|
||||
wire adc_valid_i1;
|
||||
wire adc_valid_q1;
|
||||
wire adc_dwr;
|
||||
wire adc_dsync;
|
||||
wire [ 15:0] adc_chan_i0;
|
||||
wire [ 15:0] adc_chan_q0;
|
||||
wire [ 15:0] adc_chan_i1;
|
||||
wire [ 15:0] adc_chan_q1;
|
||||
wire [ 63:0] adc_ddata;
|
||||
wire adc_dovf;
|
||||
wire dac_enable;
|
||||
|
|
@ -263,18 +278,21 @@ module system_top (
|
|||
wire dac_dunf;
|
||||
wire [111:0] dev_dbg_data;
|
||||
wire [ 61:0] dev_l_dbg_data;
|
||||
wire vga_pixel_clock;
|
||||
wire vid_v_sync;
|
||||
wire vid_h_sync;
|
||||
wire [7:0] vid_r,vid_g,vid_b;
|
||||
|
||||
// defaults
|
||||
|
||||
assign adc_drd = dac_enable & dac_valid;
|
||||
assign adc_dwr = adc_enable & adc_valid;
|
||||
|
||||
assign vga_clk = 1'd0;
|
||||
assign vga_blank_n = 1'd0;
|
||||
assign vga_sync_n = 1'd0;
|
||||
assign vga_hs = 1'd0;
|
||||
assign vga_vs = 1'd0;
|
||||
assign vga_data = 24'd0;
|
||||
|
||||
assign vga_clk = vga_pixel_clock;
|
||||
assign vga_blank_n = 1'b1;
|
||||
assign vga_sync_n = 1'b0;
|
||||
assign vga_hs = vid_h_sync;
|
||||
assign vga_vs = vid_v_sync;
|
||||
assign {vga_b,vga_g,vga_r} = {vid_b,vid_g,vid_r};
|
||||
|
||||
assign ad9361_resetb = 1'b1;
|
||||
|
||||
|
|
@ -369,15 +387,15 @@ module system_top (
|
|||
.sys_gpio_external_connection_in_port ({16'd0, 4'd0, led, push_buttons, dip_switches}),
|
||||
.sys_gpio_external_connection_out_port ({gpio_open[31:16], gpio_open[15:12], led, gpio_open[7:0]}),
|
||||
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||
.sys_hps_spim0_txd (spi_mosi),
|
||||
.sys_hps_spim0_rxd (spi_miso),
|
||||
.sys_hps_spim0_txd (),
|
||||
.sys_hps_spim0_rxd (),
|
||||
.sys_hps_spim0_ss_in_n (1'b1),
|
||||
.sys_hps_spim0_ssi_oe_n (),
|
||||
.sys_hps_spim0_ss_0_n (spi_csn),
|
||||
.sys_hps_spim0_ss_0_n (),
|
||||
.sys_hps_spim0_ss_1_n (),
|
||||
.sys_hps_spim0_ss_2_n (),
|
||||
.sys_hps_spim0_ss_3_n (),
|
||||
.sys_hps_spim0_sclk_out_clk (spi_clk),
|
||||
.sys_hps_spim0_sclk_out_clk (),
|
||||
.axi_ad9361_device_clock_clk (clk),
|
||||
.axi_ad9361_device_if_rx_clk_in_p (rx_clk_in),
|
||||
.axi_ad9361_device_if_rx_clk_in_n (1'b0),
|
||||
|
|
@ -394,18 +412,18 @@ module system_top (
|
|||
.axi_ad9361_master_if_l_clk (clk),
|
||||
.axi_ad9361_master_if_dac_sync_in (1'b0),
|
||||
.axi_ad9361_master_if_dac_sync_out (),
|
||||
.axi_ad9361_dma_if_adc_enable_i0 (adc_enable),
|
||||
.axi_ad9361_dma_if_adc_valid_i0 (adc_valid),
|
||||
.axi_ad9361_dma_if_adc_data_i0 (adc_ddata[15:0]),
|
||||
.axi_ad9361_dma_if_adc_enable_q0 (),
|
||||
.axi_ad9361_dma_if_adc_valid_q0 (),
|
||||
.axi_ad9361_dma_if_adc_data_q0 (adc_ddata[31:16]),
|
||||
.axi_ad9361_dma_if_adc_enable_i1 (),
|
||||
.axi_ad9361_dma_if_adc_valid_i1 (),
|
||||
.axi_ad9361_dma_if_adc_data_i1 (adc_ddata[47:32]),
|
||||
.axi_ad9361_dma_if_adc_enable_q1 (),
|
||||
.axi_ad9361_dma_if_adc_valid_q1 (),
|
||||
.axi_ad9361_dma_if_adc_data_q1 (adc_ddata[63:48]),
|
||||
.axi_ad9361_dma_if_adc_enable_i0 (adc_enable_i0),
|
||||
.axi_ad9361_dma_if_adc_valid_i0 (adc_valid_i0),
|
||||
.axi_ad9361_dma_if_adc_data_i0 (adc_chan_i0),
|
||||
.axi_ad9361_dma_if_adc_enable_q0 (adc_enable_q0),
|
||||
.axi_ad9361_dma_if_adc_valid_q0 (adc_valid_q0),
|
||||
.axi_ad9361_dma_if_adc_data_q0 (adc_chan_q0),
|
||||
.axi_ad9361_dma_if_adc_enable_i1 (adc_enable_i1),
|
||||
.axi_ad9361_dma_if_adc_valid_i1 (adc_valid_i1),
|
||||
.axi_ad9361_dma_if_adc_data_i1 (adc_chan_i1),
|
||||
.axi_ad9361_dma_if_adc_enable_q1 (adc_enable_q1),
|
||||
.axi_ad9361_dma_if_adc_valid_q1 (adc_valid_q1),
|
||||
.axi_ad9361_dma_if_adc_data_q1 (adc_chan_q1),
|
||||
.axi_ad9361_dma_if_adc_dovf (adc_dovf),
|
||||
.axi_ad9361_dma_if_adc_dunf (),
|
||||
.axi_ad9361_dma_if_dac_enable_i0 (dac_enable),
|
||||
|
|
@ -433,7 +451,37 @@ module system_top (
|
|||
.axi_dmac_adc_fifo_wr_if_ovf (adc_dovf),
|
||||
.axi_dmac_adc_fifo_wr_if_wren (adc_dwr),
|
||||
.axi_dmac_adc_fifo_wr_if_data (adc_ddata),
|
||||
.axi_dmac_adc_fifo_wr_if_sync (1'b1));
|
||||
.axi_dmac_adc_fifo_wr_if_sync (adc_dsync),
|
||||
.spi_ad9361_external_MISO (spi_miso),
|
||||
.spi_ad9361_external_MOSI (spi_mosi),
|
||||
.spi_ad9361_external_SCLK (spi_clk),
|
||||
.spi_ad9361_external_SS_n (spi_csn),
|
||||
.vga_pixel_clock_bridge_out_clk_clk (vga_pixel_clock),
|
||||
.vga_clock_video_output_clocked_video_vid_clk (vga_pixel_clock),
|
||||
.vga_clock_video_output_clocked_video_vid_data ({vid_r,vid_g,vid_b}),
|
||||
.vga_clock_video_output_clocked_video_underflow (),
|
||||
.vga_clock_video_output_clocked_video_vid_datavalid (),
|
||||
.vga_clock_video_output_clocked_video_vid_v_sync (vid_v_sync),
|
||||
.vga_clock_video_output_clocked_video_vid_h_sync (vid_h_sync),
|
||||
.vga_clock_video_output_clocked_video_vid_f (),
|
||||
.vga_clock_video_output_clocked_video_vid_h (),
|
||||
.vga_clock_video_output_clocked_video_vid_v (),
|
||||
.adc_pack_data_clock_clk (clk),
|
||||
.adc_pack_channels_data_chan_enable_0 (adc_enable_i0),
|
||||
.adc_pack_channels_data_chan_valid_0 (adc_valid_i0),
|
||||
.adc_pack_channels_data_chan_data_0 (adc_chan_i0),
|
||||
.adc_pack_channels_data_chan_enable_1 (adc_enable_q0),
|
||||
.adc_pack_channels_data_chan_valid_1 (adc_valid_q0),
|
||||
.adc_pack_channels_data_chan_data_1 (adc_chan_q0),
|
||||
.adc_pack_channels_data_chan_enable_2 (adc_enable_i1),
|
||||
.adc_pack_channels_data_chan_valid_2 (adc_valid_i1),
|
||||
.adc_pack_channels_data_chan_data_2 (adc_chan_i1),
|
||||
.adc_pack_channels_data_chan_enable_3 (adc_enable_q1),
|
||||
.adc_pack_channels_data_chan_valid_3 (adc_valid_q1),
|
||||
.adc_pack_channels_data_chan_data_3 (adc_chan_q1),
|
||||
.adc_pack_channels_data_dvalid (adc_dwr),
|
||||
.adc_pack_channels_data_dsync (adc_dsync),
|
||||
.adc_pack_channels_data_ddata (adc_ddata));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue