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daq2/zc706: Update to new DO storage

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Laszlo Nagy 2022-03-31 07:29:44 +01:00 committed by Laszlo Nagy
parent fa168fafe0
commit 5a33c44511
1 changed files with 3 additions and 3 deletions
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6
projects/daq2/zc706/system_bd.tcl
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@ -42,9 +42,9 @@ if {$adc_offload_type || $dac_offload_type} {
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk ad_connect axi_ddr_cntrl/ui_clk axi_rstgen/slowest_sync_clk
ad_connect axi_ddr_cntrl/ui_clk $offload_name/fifo2axi_bridge/axi_clk ad_connect axi_ddr_cntrl/ui_clk $offload_name/storage_unit/m_axi_aclk
ad_connect axi_ddr_cntrl/S_AXI $offload_name/fifo2axi_bridge/ddr_axi ad_connect axi_ddr_cntrl/S_AXI $offload_name/storage_unit/MAXI_0
ad_connect axi_rstgen/peripheral_aresetn $offload_name/fifo2axi_bridge/axi_resetn ad_connect axi_rstgen/peripheral_aresetn $offload_name/storage_unit/m_axi_aresetn
ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn ad_connect axi_rstgen/peripheral_aresetn axi_ddr_cntrl/aresetn
ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in ad_connect sys_cpu_resetn axi_rstgen/ext_reset_in