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fmcjesdadc1: Added clock constraint for the ADC path

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Adrian Costina 2016-01-22 15:46:20 +02:00
parent dca39c26f9
commit 59fbd99fdb
3 changed files with 3 additions and 1 deletions
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2
projects/fmcjesdadc1/kc705/system_constr.xdc
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@ -21,4 +21,4 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

1
projects/fmcjesdadc1/vc707/system_constr.xdc
View File

@ -21,3 +21,4 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio
# clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

1
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -21,3 +21,4 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio
# clocks
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/axi_ad9250_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]