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axi_ad9361/tdd: Update tdd related logic 

+ TDD pointers and counter width is 24
+ Change TDD control ports name to 'enable' and 'txnrx'
+ Fix constraints
+ Rx or Tx only mode is controlled by a mode enable and a operation mode specifier bit
main
Istvan Csomortani 2015-05-21 13:39:48 +03:00
parent 99f9a75dfb
commit 598ece4c8d
7 changed files with 264 additions and 351 deletions
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20
library/axi_ad9361/axi_ad9361.v
View File

@ -107,8 +107,8 @@ module axi_ad9361 (
dac_dunf,
dac_r1_mode,
tdd_enable,
tdd_txnrx,
enable,
txnrx,
// axi interface
@ -223,8 +223,8 @@ module axi_ad9361 (
input dac_dunf;
output dac_r1_mode;
output tdd_enable;
output tdd_txnrx;
output enable;
output txnrx;
// axi interface
@ -313,8 +313,8 @@ module axi_ad9361 (
wire tdd_rx_rf_en_s;
wire tdd_tx_rf_en_s;
wire [ 7:0] ad9361_tdd_status_s;
wire tdd_enable;
wire tdd_txnrx;
wire enable;
wire txnrx;
wire dac_valid_i0_s;
wire dac_valid_q0_s;
@ -387,13 +387,13 @@ module axi_ad9361 (
axi_ad9361_tdd_if #(.MODE_OF_ENABLE(1)) i_tdd_if(
.clk(clk),
.rst(tdd_rst),
.rst(rst),
.tdd_rx_vco_en(tdd_rx_vco_en_s),
.tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s),
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.ad9361_txnrx(tdd_txnrx),
.ad9361_enable(tdd_enable),
.ad9361_txnrx(txnrx),
.ad9361_enable(enable),
.ad9361_tdd_status(ad9361_tdd_status_s)
);
@ -401,7 +401,7 @@ module axi_ad9361 (
axi_ad9361_tdd i_tdd(
.clk(clk),
.rst(tdd_rst),
.rst(rst),
.tdd_enable(tdd_mode_enable_s),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en_s),

77
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -76,7 +76,7 @@ module axi_ad9361_tdd (
);
input clk;
output rst;
input rst;
// control signals from the tdd control
@ -107,54 +107,51 @@ module axi_ad9361_tdd (
// internal signals
wire rst;
wire tdd_start_s;
wire tdd_counter_reset_s;
wire tdd_enable_s;
wire tdd_secondary_s;
wire tdd_burst_en_s;
wire [ 5:0] tdd_burst_count_s;
wire tdd_continuous_tx_s;
wire tdd_continuous_rx_s;
wire [21:0] tdd_counter_init_s;
wire [21:0] tdd_frame_length_s;
wire [21:0] tdd_vco_rx_on_1_s;
wire [21:0] tdd_vco_rx_off_1_s;
wire [21:0] tdd_vco_tx_on_1_s;
wire [21:0] tdd_vco_tx_off_1_s;
wire [21:0] tdd_rx_on_1_s;
wire [21:0] tdd_rx_off_1_s;
wire [21:0] tdd_tx_on_1_s;
wire [21:0] tdd_tx_off_1_s;
wire [21:0] tdd_tx_dp_on_1_s;
wire [21:0] tdd_tx_dp_off_1_s;
wire [21:0] tdd_vco_rx_on_2_s;
wire [21:0] tdd_vco_rx_off_2_s;
wire [21:0] tdd_vco_tx_on_2_s;
wire [21:0] tdd_vco_tx_off_2_s;
wire [21:0] tdd_rx_on_2_s;
wire [21:0] tdd_rx_off_2_s;
wire [21:0] tdd_tx_on_2_s;
wire [21:0] tdd_tx_off_2_s;
wire [21:0] tdd_tx_dp_on_2_s;
wire [21:0] tdd_tx_dp_off_2_s;
wire [ 7:0] tdd_burst_count_s;
wire tdd_txnrx_only_en_s;
wire tdd_txnrx_only_s;
wire [23:0] tdd_counter_init_s;
wire [23:0] tdd_frame_length_s;
wire [23:0] tdd_vco_rx_on_1_s;
wire [23:0] tdd_vco_rx_off_1_s;
wire [23:0] tdd_vco_tx_on_1_s;
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_vco_rx_on_2_s;
wire [23:0] tdd_vco_rx_off_2_s;
wire [23:0] tdd_vco_tx_on_2_s;
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire [23:0] tdd_counter_status;
assign tdd_dbg = {tdd_counter_status, tdd_enable, tdd_tx_dp_en,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
assign tdd_enable = tdd_enable_s;
// instantiations
up_tdd_cntrl i_up_tdd_cntrl(
.clk(clk),
.tdd_enable(tdd_enable),
.tdd_start(tdd_start_s),
.tdd_rst(rst),
.tdd_counter_reset(tdd_counter_reset_s),
.rst(rst),
.tdd_enable(tdd_enable_s),
.tdd_secondary(tdd_secondary_s),
.tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_continuous_tx(tdd_continuous_tx_s),
.tdd_continuous_rx(tdd_continuous_rx_s),
.tdd_txnrx_only_en(tdd_txnrx_only_en_s),
.tdd_txnrx_only(tdd_txnrx_only_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
@ -192,15 +189,13 @@ module axi_ad9361_tdd (
ad_tdd_control i_tdd_control(
.clk(clk),
.rst(rst),
.tdd_start(tdd_start_s),
.tdd_counter_reset(tdd_counter_reset_s),
.tdd_enable(tdd_enable_s),
.tdd_secondary(tdd_secondary_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_burst_en(tdd_burst_en_s),
.tdd_burst_count(tdd_burst_count_s),
.tdd_continuous_tx(tdd_continuous_tx_s),
.tdd_continuous_rx(tdd_continuous_rx_s),
.tdd_txnrx_only_en(tdd_txnrx_only_en_s),
.tdd_txnrx_only(tdd_txnrx_only_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),

2
library/axi_ad9361/axi_ad9361_tdd_if.v
View File

@ -104,7 +104,7 @@ module axi_ad9361_tdd_if(
wire ad9361_enable_s;
// just one VCO can be enabled at a time
assign ad9361_txnrx_s = tdd_tx_vco_en;
assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en;
always @(posedge clk) begin
tdd_rx_rf_en_d <= tdd_rx_rf_en;

137
library/common/ad_tdd_control.v
View File

@ -48,39 +48,31 @@ module ad_tdd_control(
// TDD timming signals
tdd_start,
tdd_counter_reset,
tdd_enable,
tdd_secondary,
tdd_txnrx_only_en,
tdd_txnrx_only,
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_burst_en,
tdd_burst_count,
tdd_continuous_tx,
tdd_continuous_rx,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
tdd_vco_tx_off_1,
tdd_rx_on_1,
tdd_rx_off_1,
tdd_tx_on_1,
tdd_tx_off_1,
tdd_tx_dp_on_1,
tdd_tx_dp_off_1,
tdd_vco_rx_on_2,
tdd_vco_rx_off_2,
tdd_vco_tx_on_2,
tdd_vco_tx_off_2,
tdd_rx_on_2,
tdd_rx_off_2,
tdd_tx_on_2,
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
@ -104,41 +96,33 @@ module ad_tdd_control(
input clk;
input rst;
input tdd_start;
input tdd_enable;
input tdd_secondary;
input tdd_counter_reset;
input [21:0] tdd_counter_init;
input [21:0] tdd_frame_length;
input tdd_burst_en;
input [ 5:0] tdd_burst_count;
input tdd_continuous_tx;
input tdd_continuous_rx;
input [21:0] tdd_vco_rx_on_1;
input [21:0] tdd_vco_rx_off_1;
input [21:0] tdd_vco_tx_on_1;
input [21:0] tdd_vco_tx_off_1;
input [21:0] tdd_rx_on_1;
input [21:0] tdd_rx_off_1;
input [21:0] tdd_tx_on_1;
input [21:0] tdd_tx_off_1;
input [21:0] tdd_tx_dp_on_1;
input [21:0] tdd_tx_dp_off_1;
input [21:0] tdd_vco_rx_on_2;
input [21:0] tdd_vco_rx_off_2;
input [21:0] tdd_vco_tx_on_2;
input [21:0] tdd_vco_tx_off_2;
input [21:0] tdd_rx_on_2;
input [21:0] tdd_rx_off_2;
input [21:0] tdd_tx_on_2;
input [21:0] tdd_tx_off_2;
input [21:0] tdd_tx_dp_on_2;
input [21:0] tdd_tx_dp_off_2;
input tdd_txnrx_only_en;
input tdd_txnrx_only;
input [ 7:0] tdd_burst_count;
input [23:0] tdd_counter_init;
input [23:0] tdd_frame_length;
input [23:0] tdd_vco_rx_on_1;
input [23:0] tdd_vco_rx_off_1;
input [23:0] tdd_vco_tx_on_1;
input [23:0] tdd_vco_tx_off_1;
input [23:0] tdd_rx_on_1;
input [23:0] tdd_rx_off_1;
input [23:0] tdd_tx_on_1;
input [23:0] tdd_tx_off_1;
input [23:0] tdd_tx_dp_on_1;
input [23:0] tdd_tx_dp_off_1;
input [23:0] tdd_vco_rx_on_2;
input [23:0] tdd_vco_rx_off_2;
input [23:0] tdd_vco_tx_on_2;
input [23:0] tdd_vco_tx_off_2;
input [23:0] tdd_rx_on_2;
input [23:0] tdd_rx_off_2;
input [23:0] tdd_tx_on_2;
input [23:0] tdd_tx_off_2;
input [23:0] tdd_tx_dp_on_2;
input [23:0] tdd_tx_dp_off_2;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
@ -158,7 +142,7 @@ module ad_tdd_control(
// tdd counter related
reg [21:0] tdd_counter = 22'h0;
reg [23:0] tdd_counter = 24'h0;
reg [ 5:0] tdd_burst_counter = 6'h0;
reg tdd_counter_state = OFF;
@ -184,13 +168,14 @@ module ad_tdd_control(
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
reg counter_at_tdd_tx_dp_off_2 = 1'b0;
reg tdd_enable_d = 1'h0;
// internal signals
wire [21:0] tdd_tx_dp_on_1_s;
wire [21:0] tdd_tx_dp_on_2_s;
wire [21:0] tdd_tx_dp_off_1_s;
wire [21:0] tdd_tx_dp_off_2_s;
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_tx_dp_off_2_s;
assign tdd_counter_status = tdd_counter;
@ -207,13 +192,13 @@ module ad_tdd_control(
end else begin
// counter reset
if (tdd_counter_reset == 1'b1) begin
if (tdd_enable == 1'b0) begin
tdd_counter_state <= OFF;
tdd_enable_d <= tdd_enable;
end else
// start counter, the start pulse should have one clock cycle
// NOTE: a start pulse during a transaction will reinitialize the counter
if (tdd_start == 1'b1) begin
// start counter on the positive edge of the tdd_enable
if ((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
tdd_counter <= tdd_counter_init;
tdd_burst_counter <= tdd_burst_count;
tdd_counter_state <= ON;
@ -223,16 +208,15 @@ module ad_tdd_control(
if (tdd_counter_state == ON) begin
if (tdd_counter == tdd_frame_length) begin
tdd_counter <= 22'h0;
if (tdd_burst_en == 1) begin
if ( tdd_burst_counter > 0) begin // inside a burst
if ( tdd_burst_counter > 1) begin // inside a burst
tdd_burst_counter <= tdd_burst_counter - 1;
tdd_counter_state <= ON;
end
else begin // end of burst
else
if ( tdd_burst_counter == 1) begin // end of burst
tdd_burst_counter <= 6'h0;
tdd_counter_state <= OFF;
end
end
else begin // contiuous mode
tdd_burst_counter <= 6'h0;
tdd_counter_state <= ON;
@ -437,7 +421,7 @@ module ad_tdd_control(
// internal datapath delay compensation
ad_addsub #(
.A_WIDTH(22),
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_on_1_comp (
@ -449,7 +433,7 @@ module ad_tdd_control(
);
ad_addsub #(
.A_WIDTH(22),
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_on_2_comp (
@ -461,7 +445,7 @@ module ad_tdd_control(
);
ad_addsub #(
.A_WIDTH(22),
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_off_1_comp (
@ -473,7 +457,7 @@ module ad_tdd_control(
);
ad_addsub #(
.A_WIDTH(22),
.A_WIDTH(24),
.CONST_VALUE(11),
.ADD_SUB(1)
) i_tx_dp_off_2_comp (
@ -488,7 +472,10 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2 || tdd_continuous_rx) begin
if (tdd_txnrx_only_en) begin
tdd_rx_vco_en <= ~tdd_txnrx_only;
end
else if (counter_at_tdd_vco_rx_on_1 || counter_at_tdd_vco_rx_on_2) begin
tdd_rx_vco_en <= 1'b1;
end
else if (counter_at_tdd_vco_rx_off_1 || counter_at_tdd_vco_rx_off_2) begin
@ -501,7 +488,10 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2 || tdd_continuous_tx) begin
if (tdd_txnrx_only_en) begin
tdd_tx_vco_en <= tdd_txnrx_only;
end
else if (counter_at_tdd_vco_tx_on_1 || counter_at_tdd_vco_tx_on_2) begin
tdd_tx_vco_en <= 1'b1;
end
else if (counter_at_tdd_vco_tx_off_1 || counter_at_tdd_vco_tx_off_2) begin
@ -514,7 +504,10 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2 || tdd_continuous_rx) begin
if (tdd_txnrx_only_en) begin
tdd_rx_rf_en <= ~tdd_txnrx_only;
end
else if (counter_at_tdd_rx_on_1 || counter_at_tdd_rx_on_2) begin
tdd_rx_rf_en <= 1'b1;
end
else if (counter_at_tdd_rx_off_1 || counter_at_tdd_rx_off_2) begin
@ -527,7 +520,10 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2 || tdd_continuous_tx) begin
if (tdd_txnrx_only_en) begin
tdd_tx_rf_en <= tdd_txnrx_only;
end
else if (counter_at_tdd_tx_on_1 || counter_at_tdd_tx_on_2) begin
tdd_tx_rf_en <= 1'b1;
end
else if (counter_at_tdd_tx_off_1 || counter_at_tdd_tx_off_2) begin
@ -540,7 +536,10 @@ module ad_tdd_control(
always @(posedge clk) begin
if(tdd_counter_state == ON) begin
if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2 || tdd_continuous_tx) begin
if (tdd_txnrx_only_en) begin
tdd_tx_dp_en <= tdd_txnrx_only;
end
else if (counter_at_tdd_tx_dp_on_1 || counter_at_tdd_tx_dp_on_2) begin
tdd_tx_dp_en <= 1'b1;
end
else if (counter_at_tdd_tx_dp_off_1 || counter_at_tdd_tx_dp_off_2) begin

340
library/common/up_tdd_cntrl.v
View File

@ -41,18 +41,15 @@
module up_tdd_cntrl (
clk,
rst,
//rf tdd interface control
tdd_enable,
tdd_start,
tdd_rst,
tdd_counter_reset,
tdd_secondary,
tdd_burst_en,
tdd_txnrx_only_en,
tdd_txnrx_only,
tdd_burst_count,
tdd_continuous_tx,
tdd_continuous_rx,
tdd_counter_init,
tdd_frame_length,
tdd_vco_rx_on_1,
@ -97,41 +94,35 @@ module up_tdd_cntrl (
parameter PCORE_ID = 0;
input clk;
input rst;
output tdd_enable;
output tdd_start;
output tdd_rst;
output tdd_counter_reset;
output tdd_secondary;
output [21:0] tdd_counter_init;
output [21:0] tdd_frame_length;
output tdd_burst_en;
output [ 5:0] tdd_burst_count;
output tdd_continuous_tx;
output tdd_continuous_rx;
output [21:0] tdd_vco_rx_on_1;
output [21:0] tdd_vco_rx_off_1;
output [21:0] tdd_vco_tx_on_1;
output [21:0] tdd_vco_tx_off_1;
output [21:0] tdd_rx_on_1;
output [21:0] tdd_rx_off_1;
output [21:0] tdd_tx_on_1;
output [21:0] tdd_tx_off_1;
output [21:0] tdd_tx_dp_on_1;
output [21:0] tdd_tx_dp_off_1;
output [21:0] tdd_vco_rx_on_2;
output [21:0] tdd_vco_rx_off_2;
output [21:0] tdd_vco_tx_on_2;
output [21:0] tdd_vco_tx_off_2;
output [21:0] tdd_rx_on_2;
output [21:0] tdd_rx_off_2;
output [21:0] tdd_tx_on_2;
output [21:0] tdd_tx_off_2;
output [21:0] tdd_tx_dp_on_2;
output [21:0] tdd_tx_dp_off_2;
output tdd_txnrx_only_en;
output tdd_txnrx_only;
output [ 7:0] tdd_burst_count;
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
output [23:0] tdd_vco_rx_on_1;
output [23:0] tdd_vco_rx_off_1;
output [23:0] tdd_vco_tx_on_1;
output [23:0] tdd_vco_tx_off_1;
output [23:0] tdd_rx_on_1;
output [23:0] tdd_rx_off_1;
output [23:0] tdd_tx_on_1;
output [23:0] tdd_tx_off_1;
output [23:0] tdd_tx_dp_on_1;
output [23:0] tdd_tx_dp_off_1;
output [23:0] tdd_vco_rx_on_2;
output [23:0] tdd_vco_rx_off_2;
output [23:0] tdd_vco_tx_on_2;
output [23:0] tdd_vco_tx_off_2;
output [23:0] tdd_rx_on_2;
output [23:0] tdd_rx_off_2;
output [23:0] tdd_tx_on_2;
output [23:0] tdd_tx_off_2;
output [23:0] tdd_tx_dp_on_2;
output [23:0] tdd_tx_dp_off_2;
input [ 7:0] tdd_status;
@ -152,51 +143,43 @@ module up_tdd_cntrl (
reg up_wack = 1'h0;
reg [31:0] up_scratch = 32'h0;
reg up_resetn = 1'h0;
reg up_rack = 1'h0;
reg [31:0] up_rdata = 32'h0;
reg up_tdd_enable = 1'h0;
reg up_tdd_start = 1'h0;
reg up_tdd_counter_reset = 1'h0;
reg up_tdd_secondary = 1'h0;
reg [21:0] up_tdd_counter_init = 22'h0;
reg [21:0] up_tdd_frame_length = 22'h0;
reg up_tdd_txnrx_only_en = 1'h0;
reg up_tdd_txnrx_only = 1'h0;
reg up_tdd_burst_en = 1'h0;
reg [ 5:0] up_tdd_burst_count = 6'h0;
reg up_tdd_continuous_tx = 1'h0;
reg up_tdd_continuous_rx = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
reg [23:0] up_tdd_frame_length = 24'h0;
reg [21:0] up_tdd_vco_rx2tx_1 = 22'h0;
reg [21:0] up_tdd_vco_tx2rx_1 = 22'h0;
reg [21:0] up_tdd_vco_rx_on_1 = 22'h0;
reg [21:0] up_tdd_vco_rx_off_1 = 22'h0;
reg [21:0] up_tdd_vco_tx_on_1 = 22'h0;
reg [21:0] up_tdd_vco_tx_off_1 = 22'h0;
reg [21:0] up_tdd_rx_on_1 = 22'h0;
reg [21:0] up_tdd_rx_off_1 = 22'h0;
reg [21:0] up_tdd_tx_on_1 = 22'h0;
reg [21:0] up_tdd_tx_off_1 = 22'h0;
reg [21:0] up_tdd_tx_dp_on_1 = 22'h0;
reg [21:0] up_tdd_tx_dp_off_1 = 22'h0;
reg [21:0] up_tdd_vco_rx_on_2 = 22'h0;
reg [21:0] up_tdd_vco_rx_off_2 = 22'h0;
reg [21:0] up_tdd_vco_tx_on_2 = 22'h0;
reg [21:0] up_tdd_vco_tx_off_2 = 22'h0;
reg [21:0] up_tdd_rx_on_2 = 22'h0;
reg [21:0] up_tdd_rx_off_2 = 22'h0;
reg [21:0] up_tdd_tx_on_2 = 22'h0;
reg [21:0] up_tdd_tx_off_2 = 22'h0;
reg [21:0] up_tdd_tx_dp_on_2 = 22'h0;
reg [21:0] up_tdd_tx_dp_off_2 = 22'h0;
reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
reg [23:0] up_tdd_rx_on_1 = 24'h0;
reg [23:0] up_tdd_rx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_on_1 = 24'h0;
reg [23:0] up_tdd_tx_off_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
reg [23:0] up_tdd_rx_on_2 = 24'h0;
reg [23:0] up_tdd_rx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_on_2 = 24'h0;
reg [23:0] up_tdd_tx_off_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire tdd_rst;
wire up_cntrl_xfer_done;
wire [ 7:0] up_tdd_status_s;
@ -205,7 +188,6 @@ module up_tdd_cntrl (
assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
@ -213,127 +195,107 @@ module up_tdd_cntrl (
if (up_rstn == 0) begin
up_wack <= 1'h0;
up_scratch <= 32'h0;
up_resetn <= 1'h0;
up_tdd_start <= 1'h0;
up_tdd_counter_reset <= 1'h0;
up_tdd_enable <= 1'h0;
up_tdd_secondary <= 1'h0;
up_tdd_counter_init <= 22'h0;
up_tdd_frame_length <= 22'h0;
up_tdd_burst_en <= 1'h0;
up_tdd_continuous_rx <= 1'h0;
up_tdd_continuous_tx <= 1'h0;
up_tdd_burst_count <= 6'h0;
up_tdd_vco_rx_on_1 <= 22'h0;
up_tdd_vco_rx_off_1 <= 22'h0;
up_tdd_vco_tx_on_1 <= 22'h0;
up_tdd_vco_tx_off_1 <= 22'h0;
up_tdd_rx_on_1 <= 22'h0;
up_tdd_rx_off_1 <= 22'h0;
up_tdd_tx_on_1 <= 22'h0;
up_tdd_tx_off_1 <= 22'h0;
up_tdd_tx_dp_on_1 <= 22'h0;
up_tdd_vco_rx_on_2 <= 22'h0;
up_tdd_vco_rx_off_2 <= 22'h0;
up_tdd_vco_tx_on_2 <= 22'h0;
up_tdd_vco_tx_off_2 <= 22'h0;
up_tdd_rx_on_2 <= 22'h0;
up_tdd_rx_off_2 <= 22'h0;
up_tdd_tx_on_2 <= 22'h0;
up_tdd_tx_off_2 <= 22'h0;
up_tdd_tx_dp_on_2 <= 22'h0;
up_tdd_txnrx_only_en <= 1'h0;
up_tdd_txnrx_only <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
up_tdd_vco_rx_on_1 <= 24'h0;
up_tdd_vco_rx_off_1 <= 24'h0;
up_tdd_vco_tx_on_1 <= 24'h0;
up_tdd_vco_tx_off_1 <= 24'h0;
up_tdd_rx_on_1 <= 24'h0;
up_tdd_rx_off_1 <= 24'h0;
up_tdd_tx_on_1 <= 24'h0;
up_tdd_tx_off_1 <= 24'h0;
up_tdd_tx_dp_on_1 <= 24'h0;
up_tdd_vco_rx_on_2 <= 24'h0;
up_tdd_vco_rx_off_2 <= 24'h0;
up_tdd_vco_tx_on_2 <= 24'h0;
up_tdd_vco_tx_off_2 <= 24'h0;
up_tdd_rx_on_2 <= 24'h0;
up_tdd_rx_off_2 <= 24'h0;
up_tdd_tx_on_2 <= 24'h0;
up_tdd_tx_off_2 <= 24'h0;
up_tdd_tx_dp_on_2 <= 24'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
up_tdd_txnrx_only_en <= up_wdata[2];
up_tdd_txnrx_only <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_enable <= up_wdata[0];
end
if (up_tdd_start == 1) begin
if (up_cntrl_xfer_done == 1) begin
up_tdd_start <= 1'h0;
up_tdd_counter_reset <= 1'h0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_tdd_counter_reset <= up_wdata[2];
up_tdd_start <= up_wdata[1];
up_tdd_burst_count <= up_wdata[7:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
up_tdd_burst_count <= up_wdata[21:16];
up_tdd_continuous_rx <= up_wdata[3];
up_tdd_continuous_tx <= up_wdata[2];
up_tdd_burst_en <= up_wdata[1];
up_tdd_secondary <= up_wdata[0];
up_tdd_counter_init <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_tdd_counter_init <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_frame_length <= up_wdata[21:0];
up_tdd_frame_length <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_1 <= up_wdata[21:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_1 <= up_wdata[21:0];
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_1 <= up_wdata[21:0];
up_tdd_vco_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
up_tdd_rx_on_1 <= up_wdata[21:0];
up_tdd_rx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
up_tdd_rx_off_1 <= up_wdata[21:0];
up_tdd_rx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
up_tdd_tx_on_1 <= up_wdata[21:0];
up_tdd_tx_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
up_tdd_tx_off_1 <= up_wdata[21:0];
up_tdd_tx_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_tdd_tx_dp_on_1 <= up_wdata[21:0];
up_tdd_tx_dp_on_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_tdd_tx_dp_off_1 <= up_wdata[21:0];
up_tdd_tx_dp_off_1 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_2 <= up_wdata[21:0];
up_tdd_vco_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_tdd_vco_rx_off_2 <= up_wdata[21:0];
up_tdd_vco_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_tdd_vco_tx_on_2 <= up_wdata[21:0];
up_tdd_vco_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
up_tdd_vco_tx_off_2 <= up_wdata[21:0];
up_tdd_vco_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
up_tdd_rx_on_2 <= up_wdata[21:0];
up_tdd_rx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
up_tdd_rx_off_2 <= up_wdata[21:0];
up_tdd_rx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
up_tdd_tx_on_2 <= up_wdata[21:0];
up_tdd_tx_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
up_tdd_tx_off_2 <= up_wdata[21:0];
up_tdd_tx_off_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
up_tdd_tx_dp_on_2 <= up_wdata[21:0];
up_tdd_tx_dp_on_2 <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
up_tdd_tx_dp_off_2 <= up_wdata[21:0];
up_tdd_tx_dp_off_2 <= up_wdata[23:0];
end
end
end
@ -348,77 +310,59 @@ module up_tdd_cntrl (
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'h0, up_resetn};
8'h11: up_rdata <= {29'h0, up_tdd_counter_reset, up_tdd_start, up_tdd_enable};
8'h12: up_rdata <= {10'h0, up_tdd_burst_count, 12'h0, up_tdd_continuous_rx, up_tdd_continuous_tx, up_tdd_burst_en, up_tdd_secondary};
8'h13: up_rdata <= {10'h0, up_tdd_counter_init};
8'h14: up_rdata <= {10'h0, up_tdd_frame_length};
8'h1A: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= {10'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= {10'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= {10'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= {10'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= {10'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= {10'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= {10'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= {10'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= {10'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= {10'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= {10'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= {10'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= {10'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= {10'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= {10'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= {10'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= {10'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= {10'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= {10'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= {10'h0, up_tdd_tx_dp_off_2};
8'h10: up_rdata <= {28'h0, up_tdd_txnrx_only, up_tdd_txnrx_only_en, up_tdd_secondary, up_tdd_enable};
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= {8'h0, up_tdd_counter_init};
8'h13: up_rdata <= {8'h0, up_tdd_frame_length};
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= {8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= {8'h0, up_tdd_vco_rx_off_1};
8'h22: up_rdata <= {8'h0, up_tdd_vco_tx_on_1};
8'h23: up_rdata <= {8'h0, up_tdd_vco_tx_off_1};
8'h24: up_rdata <= {8'h0, up_tdd_rx_on_1};
8'h25: up_rdata <= {8'h0, up_tdd_rx_off_1};
8'h26: up_rdata <= {8'h0, up_tdd_tx_on_1};
8'h27: up_rdata <= {8'h0, up_tdd_tx_off_1};
8'h28: up_rdata <= {8'h0, up_tdd_tx_dp_on_1};
8'h29: up_rdata <= {8'h0, up_tdd_tx_dp_off_1};
8'h30: up_rdata <= {8'h0, up_tdd_vco_rx_on_2};
8'h31: up_rdata <= {8'h0, up_tdd_vco_rx_off_2};
8'h32: up_rdata <= {8'h0, up_tdd_vco_tx_on_2};
8'h33: up_rdata <= {8'h0, up_tdd_vco_tx_off_2};
8'h34: up_rdata <= {8'h0, up_tdd_rx_on_2};
8'h35: up_rdata <= {8'h0, up_tdd_rx_off_2};
8'h36: up_rdata <= {8'h0, up_tdd_tx_on_2};
8'h37: up_rdata <= {8'h0, up_tdd_tx_off_2};
8'h38: up_rdata <= {8'h0, up_tdd_tx_dp_on_2};
8'h39: up_rdata <= {8'h0, up_tdd_tx_dp_off_2};
default: up_rdata <= 32'h0;
endcase
end
end
end
// resets
ad_rst i_rf_rst_reg (
.preset(up_preset_s),
.clk(clk),
.rst(tdd_rst)
);
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(13)) i_tdd_control (
up_xfer_cntrl #(.DATA_WIDTH(12)) i_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
up_tdd_counter_reset,
up_tdd_secondary,
up_tdd_start,
up_tdd_burst_en,
up_tdd_continuous_tx,
up_tdd_continuous_rx,
up_tdd_txnrx_only_en,
up_tdd_txnrx_only,
up_tdd_burst_count
}),
.up_xfer_done(up_cntrl_xfer_done),
.d_rst(tdd_rst),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_enable,
tdd_counter_reset,
tdd_secondary,
tdd_start,
tdd_burst_en,
tdd_continuous_tx,
tdd_continuous_rx,
tdd_txnrx_only_en,
tdd_txnrx_only,
tdd_burst_count
}));
up_xfer_cntrl #(.DATA_WIDTH(484)) i_tdd_counter_values (
up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_counter_init,
@ -445,7 +389,7 @@ module up_tdd_cntrl (
up_tdd_tx_dp_off_2
}),
.up_xfer_done(),
.d_rst(tdd_rst),
.d_rst(rst),
.d_clk(clk),
.d_data_cntrl({tdd_counter_init,
tdd_frame_length,
@ -476,7 +420,7 @@ module up_tdd_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status (up_tdd_status_s),
.d_rst (tdd_rst),
.d_rst (rst),
.d_clk (clk),
.d_data_status (tdd_status));

27
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -74,8 +74,8 @@ ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
ad_connect axi_ad9361/enable enable
ad_connect axi_ad9361/txnrx txnrx
ad_connect enable axi_ad9361/enable
ad_connect txnrx axi_ad9361/txnrx
ad_connect axi_ad9361_clk util_adc_pack/clk
ad_connect axi_ad9361/adc_valid_i0 util_adc_pack/chan_valid_0
ad_connect axi_ad9361/adc_valid_q0 util_adc_pack/chan_valid_1
@ -123,34 +123,11 @@ ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
set ila_tdd [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_tdd]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_tdd
set_property -dict [list CONFIG.C_NUM_OF_PROBES {7}] $ila_tdd
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_tdd
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE2_WIDTH {35}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE3_WIDTH {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE5_WIDTH {1}] $ila_tdd
set_property -dict [list CONFIG.C_PROBE6_WIDTH {64}] $ila_tdd
ad_connect axi_ad9361_clk ila_tdd/clk
ad_connect axi_ad9361/enable ila_tdd/probe0
ad_connect axi_ad9361/txnrx ila_tdd/probe1
ad_connect axi_ad9361/tdd_dbg ila_tdd/probe2
ad_connect util_dac_unpack/fifo_valid ila_tdd/probe3
ad_connect util_dac_unpack/dma_rd ila_tdd/probe4
ad_connect axi_ad9361/dac_dunf ila_tdd/probe5
ad_connect util_dac_unpack/dma_data ila_tdd/probe6
# ila (adc)
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_adc]

2
projects/fmcomms2/zc706/system_constr.xdc
View File

@ -65,8 +65,6 @@ set_property -dict {PACKAGE_PIN AK21 IOSTANDARD LVCMOS25} [get_ports sp
set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS25} [get_ports spi_udc_sclk] ; ## PMOD1_3_LS
set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS25} [get_ports spi_udc_data] ; ## PMOD1_2_LS
set_property -dict {IOB TRUE} [get_ports {enable txnrx}]
# clocks
create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p]