zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

resolving conflicts

main
Rejeesh Kutty 2017-05-17 16:18:53 -04:00
parent 6649b23bc8
commit 598bd7e226
2 changed files with 94 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
library/util_adcfifo/util_adcfifo.v
View File

@ -25,6 +25,7 @@
module util_adcfifo #(
parameter DEVICE_TYPE = 0,
parameter ADC_DATA_WIDTH = 256,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_READY_ENABLE = 1,
@ -32,52 +33,55 @@ module util_adcfifo #(
// fifo interface
input adc_rst,
input adc_clk,
input adc_wr,
input [ADC_DATA_WIDTH-1:0] adc_wdata,
output adc_wovf,
input adc_rst,
input adc_clk,
input adc_wr,
input [ADC_DATA_WIDTH-1:0] adc_wdata,
output adc_wovf,
// dma interface
input dma_clk,
output dma_wr,
output [DMA_DATA_WIDTH-1:0] dma_wdata,
input dma_wready,
input dma_xfer_req,
output [ 3:0] dma_xfer_status);
input dma_clk,
output dma_wr,
output [DMA_DATA_WIDTH-1:0] dma_wdata,
input dma_wready,
input dma_xfer_req,
output [ 3:0] dma_xfer_status);
localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH;
localparam ADC_ADDRESS_WIDTH = (DMA_MEM_RATIO == 1) ? (DMA_ADDRESS_WIDTH) : (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3));
localparam ADC_ADDRESS_WIDTH = (DMA_MEM_RATIO == 1) ? (DMA_ADDRESS_WIDTH) :
(DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) :
(DMA_ADDRESS_WIDTH - 3));
localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1;
localparam DMA_ADDR_LIMIT = (2**DMA_ADDRESS_WIDTH)-1;
// internal registers
reg [ 2:0] adc_xfer_req_m = 'd0;
reg adc_xfer_init = 'd0;
reg adc_xfer_enable = 'd0;
reg adc_wr_int = 'd0;
reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0;
reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0;
reg adc_waddr_rel_t = 'd0;
reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_rel = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [ADC_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] adc_xfer_req_m = 'd0;
reg adc_xfer_init = 'd0;
reg adc_xfer_enable = 'd0;
reg adc_wr_int = 'd0;
reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0;
reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0;
reg adc_waddr_rel_t = 'd0;
reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_rel = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [ADC_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;
// internal signals
wire dma_waddr_rel_t_s;
wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
@ -136,8 +140,10 @@ module util_adcfifo #(
assign dma_xfer_status = 4'd0;
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 1) ? dma_waddr_rel : (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 1) ? dma_waddr_rel :
(DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} :
{dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
@ -154,7 +160,7 @@ module util_adcfifo #(
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr < ADC_ADDR_LIMIT) ? ((dma_raddr >= dma_waddr_rel_s) ? 1'b0 : dma_wready_s) : dma_wready_s ;
assign dma_rd_s = (dma_raddr < dma_waddr_rel_s) ? dma_wready_s : 1'b0;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
@ -167,7 +173,7 @@ module util_adcfifo #(
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
if (dma_raddr < ADC_ADDR_LIMIT) begin
if (dma_raddr < DMA_ADDR_LIMIT) begin
dma_raddr <= dma_raddr + 1'b1;
end
end
@ -176,6 +182,17 @@ module util_adcfifo #(
// instantiations
generate
if (DEVICE_TYPE == 1) begin
alt_mem_asym i_mem_asym (
.mem_i_wrclock (adc_clk),
.mem_i_wren (adc_wr_int),
.mem_i_wraddress (adc_waddr_int),
.mem_i_datain (adc_wdata_int),
.mem_i_rdclock (dma_clk),
.mem_i_rdaddress (dma_raddr),
.mem_o_dataout (dma_rdata_s));
end else begin
ad_mem_asym #(
.A_ADDRESS_WIDTH (ADC_ADDRESS_WIDTH),
.A_DATA_WIDTH (ADC_DATA_WIDTH),
@ -189,6 +206,8 @@ module util_adcfifo #(
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
end
endgenerate
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),

52
library/util_adcfifo/util_adcfifo_hw.tcl
View File

@ -1,12 +1,14 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}
set_module_property ELABORATION_CALLBACK p_util_adcfifo
# files
ad_ip_files util_adcfifo [list\
$ad_hdl_dir/library/altera/common/ad_mem_asym.v \
$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
util_adcfifo.v \
util_adcfifo_constr.sdc]
@ -14,23 +16,45 @@ ad_ip_files util_adcfifo [list\
# parameters
ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
ad_ip_parameter DEVICE_TYPE INTEGER 1
ad_ip_parameter ADC_DATA_WIDTH INTEGER 256
ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
ad_ip_parameter DMA_READY_ENABLE INTEGER 1
ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10
# interfaces
# elaborate
ad_alt_intf clock adc_clk input 1 adc_clk
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_wr input 1 valid
ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
ad_alt_intf signal adc_wovf output 1 ovf
proc p_util_adcfifo {} {
ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf signal dma_wr output 1 valid
ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data
ad_alt_intf signal dma_wready input 1 ready
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_alt_intf signal dma_xfer_status output 4 xfer_status
# read parameters
set m_device_family [get_parameter_value "DEVICE_FAMILY"]
set m_adc_data_width [get_parameter_value "ADC_DATA_WIDTH"]
set m_dma_addr_width [get_parameter_value "DMA_ADDRESS_WIDTH"]
set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
# altera memory
add_hdl_instance alt_mem_asym alt_mem_asym
set_instance_parameter_value alt_mem_asym DEVICE_FAMILY $m_device_family
set_instance_parameter_value alt_mem_asym A_ADDRESS_WIDTH 0
set_instance_parameter_value alt_mem_asym A_DATA_WIDTH $m_adc_data_width
set_instance_parameter_value alt_mem_asym B_ADDRESS_WIDTH $m_dma_addr_width
set_instance_parameter_value alt_mem_asym B_DATA_WIDTH $m_dma_data_width
# interfaces
ad_alt_intf clock adc_clk input 1 adc_clk
ad_alt_intf reset adc_rst input 1 if_adc_clk
ad_alt_intf signal adc_wr input 1 valid
ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
ad_alt_intf signal adc_wovf output 1 ovf
ad_alt_intf clock dma_clk input 1 clk
ad_alt_intf signal dma_wr output 1 valid
ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data
ad_alt_intf signal dma_wready input 1 ready
ad_alt_intf signal dma_xfer_req input 1 xfer_req
ad_alt_intf signal dma_xfer_status output 4 xfer_status
}