axi_adrv9001: Export TDD mode
parent
18b2a8b0a7
commit
58f2eec127
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@ -155,6 +155,7 @@ module axi_adrv9001 #(
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// TDD interface
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input tdd_sync,
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output tdd_sync_cntr,
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input gpio_rx1_enable_in,
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input gpio_rx2_enable_in,
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@ -473,6 +474,7 @@ module axi_adrv9001 #(
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// TDD interface
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.tdd_sync (tdd_sync),
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.tdd_sync_cntr (tdd_sync_cntr),
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.tdd_rx1_rf_en (tdd_rx1_rf_en),
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.tdd_tx1_rf_en (tdd_tx1_rf_en),
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.tdd_if1_mode (tdd_if1_mode),
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@ -143,6 +143,7 @@ module axi_ad9001_core #(
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// TDD interface
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input tdd_sync,
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output tdd_sync_cntr,
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output tdd_rx1_rf_en,
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output tdd_tx1_rf_en,
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@ -536,7 +537,7 @@ module axi_ad9001_core #(
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.tdd_enabled (tdd_if1_mode),
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.tdd_status (8'h0),
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.tdd_sync (tdd_sync),
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.tdd_sync_cntr (),
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.tdd_sync_cntr (tdd_sync_cntr1),
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.tdd_tx_valid (tdd_tx1_valid),
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.tdd_rx_valid (tdd_rx1_valid),
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.up_rstn (up_rstn),
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@ -562,7 +563,7 @@ module axi_ad9001_core #(
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.tdd_enabled (tdd_if2_mode_loc),
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.tdd_status (8'h0),
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.tdd_sync (tdd_sync),
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.tdd_sync_cntr (),
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.tdd_sync_cntr (tdd_sync_cntr2),
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.tdd_tx_valid (tdd_tx2_valid),
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.tdd_rx_valid (tdd_rx2_valid),
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.up_rstn (up_rstn),
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@ -580,6 +581,8 @@ module axi_ad9001_core #(
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assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en;
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assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode;
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assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2;
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end else begin
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assign up_wack_s[6] = 1'b0;
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assign up_rack_s[6] = 1'b0;
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