axi_adc_trigger: Use valid in data delay stage

This is required to match the delays in the data path to internal/external
trigger path.

library/axi_adc_trigger/axi_adc_trigger.v

@@ -310,8 +310,10 @@ module axi_adc_trigger #(
   assign trigger_out = trigger_out_m2;
 
   always @(posedge clk) begin
-    data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]};
-    data_b_trig <= (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]};
+    if (data_out_valid) begin
+      data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]};
+      data_b_trig <= (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]};
+    end
 
     data_valid_a_trig <= data_valid_a;
     data_valid_b_trig <= data_valid_b;