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axi_adc_trigger: Use valid in data delay stage 

This is required to match the delays in the data path to internal/external
trigger path.
main
AndreiGrozav 2020-05-06 16:03:48 +03:00 committed by AndreiGrozav
parent 4766d01915
commit 58e0044643
1 changed files with 4 additions and 2 deletions
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2
library/axi_adc_trigger/axi_adc_trigger.v
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@ -310,8 +310,10 @@ module axi_adc_trigger #(
assign trigger_out = trigger_out_m2; assign trigger_out = trigger_out_m2;
always @(posedge clk) begin always @(posedge clk) begin
if (data_out_valid) begin
data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]}; data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]};
data_b_trig <= (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]}; data_b_trig <= (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]};
end
data_valid_a_trig <= data_valid_a; data_valid_a_trig <= data_valid_a;
data_valid_b_trig <= data_valid_b; data_valid_b_trig <= data_valid_b;