diff --git a/library/axi_ad9361/axi_ad9361.v b/library/axi_ad9361/axi_ad9361.v index bc96169d7..9d2365831 100644 --- a/library/axi_ad9361/axi_ad9361.v +++ b/library/axi_ad9361/axi_ad9361.v @@ -39,7 +39,7 @@ module axi_ad9361 ( - // physical interface (receive) + // physical interface (receive-lvds) rx_clk_in_p, rx_clk_in_n, @@ -48,7 +48,13 @@ module axi_ad9361 ( rx_data_in_p, rx_data_in_n, - // physical interface (transmit) + // physical interface (receive-cmos) + + rx_clk_in, + rx_frame_in, + rx_data_in, + + // physical interface (transmit-lvds) tx_clk_out_p, tx_clk_out_n, @@ -57,6 +63,12 @@ module axi_ad9361 ( tx_data_out_p, tx_data_out_n, + // physical interface (transmit-cmos) + + tx_clk_out, + tx_frame_out, + tx_data_out, + // ensm control enable, @@ -157,12 +169,13 @@ module axi_ad9361 ( parameter ID = 0; parameter DEVICE_TYPE = 0; + parameter CMOS_OR_LVDS_N = 0; parameter DAC_IODELAY_ENABLE = 0; parameter IO_DELAY_GROUP = "dev_if_delay_group"; parameter DAC_DATAPATH_DISABLE = 0; parameter ADC_DATAPATH_DISABLE = 0; - // physical interface (receive) + // physical interface (receive-lvds) input rx_clk_in_p; input rx_clk_in_n; @@ -171,7 +184,13 @@ module axi_ad9361 ( input [ 5:0] rx_data_in_p; input [ 5:0] rx_data_in_n; - // physical interface (transmit) + // physical interface (receive-cmos) + + input rx_clk_in; + input rx_frame_in; + input [11:0] rx_data_in; + + // physical interface (transmit-lvds) output tx_clk_out_p; output tx_clk_out_n; @@ -180,6 +199,12 @@ module axi_ad9361 ( output [ 5:0] tx_data_out_p; output [ 5:0] tx_data_out_n; + // physical interface (transmit-cmos) + + output tx_clk_out; + output tx_frame_out; + output [11:0] tx_data_out; + // ensm control output enable; @@ -281,13 +306,11 @@ module axi_ad9361 ( reg up_wack = 'd0; reg up_rack = 'd0; reg [31:0] up_rdata = 'd0; - reg [15:0] adc_data_i0 = 16'b0; reg [15:0] adc_data_q0 = 16'b0; reg [15:0] adc_data_i1 = 16'b0; reg [15:0] adc_data_q1 = 16'b0; - // internal clocks and resets wire up_clk; @@ -307,12 +330,12 @@ module axi_ad9361 ( wire dac_valid_q0_s; wire dac_valid_i1_s; wire dac_valid_q1_s; - wire [ 6:0] up_adc_dld_s; - wire [34:0] up_adc_dwdata_s; - wire [34:0] up_adc_drdata_s; - wire [ 9:0] up_dac_dld_s; - wire [49:0] up_dac_dwdata_s; - wire [49:0] up_dac_drdata_s; + wire [12:0] up_adc_dld_s; + wire [64:0] up_adc_dwdata_s; + wire [64:0] up_adc_drdata_s; + wire [15:0] up_dac_dld_s; + wire [79:0] up_dac_dwdata_s; + wire [79:0] up_dac_drdata_s; wire delay_locked_s; wire up_wreq_s; wire [13:0] up_waddr_s; @@ -337,7 +360,6 @@ module axi_ad9361 ( wire tdd_enable_s; wire tdd_txnrx_s; wire tdd_mode_s; - wire [15:0] adc_data_i0_s; wire [15:0] adc_data_q0_s; wire [15:0] adc_data_i1_s; @@ -364,6 +386,67 @@ module axi_ad9361 ( // device interface + generate + if (CMOS_OR_LVDS_N == 1) begin + + assign tx_clk_out_p = 1'd0; + assign tx_clk_out_n = 1'd1; + assign tx_frame_out_p = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_p = 6'h00; + assign tx_data_out_n = 6'h3f; + + axi_ad9361_cmos_if #( + .DEVICE_TYPE (DEVICE_TYPE), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP)) + i_dev_if ( + .rx_clk_in (rx_clk_in), + .rx_frame_in (rx_frame_in), + .rx_data_in (rx_data_in), + .tx_clk_out (tx_clk_out), + .tx_frame_out (tx_frame_out), + .tx_data_out (tx_data_out), + .enable (enable), + .txnrx (txnrx), + .rst (rst), + .clk (clk), + .l_clk (l_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .adc_r1_mode (adc_r1_mode), + .adc_ddr_edgesel (adc_ddr_edgesel), + .dac_valid (g_dac_valid_s), + .dac_data (dac_data_s), + .dac_r1_mode (dac_r1_mode), + .tdd_enable (tdd_enable_s), + .tdd_txnrx (tdd_txnrx_s), + .tdd_mode (tdd_mode_s), + .up_clk (up_clk), + .up_enable (up_enable), + .up_txnrx (up_txnrx), + .up_adc_dld (up_adc_dld_s), + .up_adc_dwdata (up_adc_dwdata_s), + .up_adc_drdata (up_adc_drdata_s), + .up_dac_dld (up_dac_dld_s), + .up_dac_dwdata (up_dac_dwdata_s), + .up_dac_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + end + endgenerate + + generate + if (CMOS_OR_LVDS_N == 0) begin + + assign tx_clk_out = 1'd0; + assign tx_frame_out = 1'd0; + assign tx_data_out = 12'd0; + assign up_adc_drdata_s[64:35] = 30'd0; + assign up_dac_drdata_s[79:50] = 30'd0; + axi_ad9361_dev_if #( .DEVICE_TYPE (DEVICE_TYPE), .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), @@ -400,19 +483,22 @@ module axi_ad9361 ( .up_clk (up_clk), .up_enable (up_enable), .up_txnrx (up_txnrx), - .up_adc_dld (up_adc_dld_s), - .up_adc_dwdata (up_adc_dwdata_s), - .up_adc_drdata (up_adc_drdata_s), - .up_dac_dld (up_dac_dld_s), - .up_dac_dwdata (up_dac_dwdata_s), - .up_dac_drdata (up_dac_drdata_s), + .up_adc_dld (up_adc_dld_s[6:0]), + .up_adc_dwdata (up_adc_dwdata_s[34:0]), + .up_adc_drdata (up_adc_drdata_s[34:0]), + .up_dac_dld (up_dac_dld_s[9:0]), + .up_dac_dwdata (up_dac_dwdata_s[49:0]), + .up_dac_drdata (up_dac_drdata_s[49:0]), .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked_s)); + end + endgenerate // TDD interface // additional flop to keep control and data synced + always @(posedge clk) begin adc_data_i0 <= adc_data_i0_s; adc_data_q0 <= adc_data_q0_s; diff --git a/library/axi_ad9361/axi_ad9361_cmos_if.v b/library/axi_ad9361/axi_ad9361_cmos_if.v index 609dcc226..a3dcf6f59 100644 --- a/library/axi_ad9361/axi_ad9361_cmos_if.v +++ b/library/axi_ad9361/axi_ad9361_cmos_if.v @@ -247,8 +247,8 @@ module axi_ad9361_cmos_if ( // receive data path for dual rf, frame is expected to qualify iq for rf-1 only always @(posedge l_clk) begin - rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || - (rx_frame_4_s == 4'b1001)) ? 1'b0 : 1'b1; + rx_error_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1100) || + (rx_frame_4_s == 4'b1001) || (rx_frame_4_s == 4'b0110)) ? 1'b0 : 1'b1; rx_valid_r2 <= ((rx_frame_4_s == 4'b0011) || (rx_frame_4_s == 4'b1001)) ? 1'b1 : 1'b0; case (rx_frame_s) @@ -311,13 +311,13 @@ module axi_ad9361_cmos_if ( tx_data <= dac_data; end case (tx_data_sel_s) - 3'b100: begin + 3'b101: begin tx_frame_p <= 1'b0; tx_frame_n <= 1'b0; tx_data_p <= tx_data[35:24]; tx_data_n <= tx_data[47:36]; end - 3'b101: begin + 3'b100: begin tx_frame_p <= 1'b1; tx_frame_n <= 1'b1; tx_data_p <= tx_data[11: 0]; @@ -428,7 +428,7 @@ module axi_ad9361_cmos_if ( .IODELAY_GROUP (IO_DELAY_GROUP)) i_rx_frame ( .rx_clk (l_clk), - .rx_data_in_p (rx_frame_in), + .rx_data_in (rx_frame_in), .rx_data_p (rx_frame_p_s), .rx_data_n (rx_frame_n_s), .up_clk (up_clk), @@ -495,8 +495,8 @@ module axi_ad9361_cmos_if ( .IODELAY_GROUP (IO_DELAY_GROUP)) i_tx_clk ( .tx_clk (l_clk), - .tx_data_p (1'b0), - .tx_data_n (1'b1), + .tx_data_p (1'b1), + .tx_data_n (1'b0), .tx_data_out (tx_clk_out), .up_clk (up_clk), .up_dld (up_dac_dld[13]), diff --git a/library/axi_ad9361/axi_ad9361_ip.tcl b/library/axi_ad9361/axi_ad9361_ip.tcl index 72f0c8e60..9a3d0c65c 100755 --- a/library/axi_ad9361/axi_ad9361_ip.tcl +++ b/library/axi_ad9361/axi_ad9361_ip.tcl @@ -10,6 +10,9 @@ adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ "$ad_hdl_dir/library/common/ad_lvds_in.v" \ "$ad_hdl_dir/library/common/ad_lvds_out.v" \ + "$ad_hdl_dir/library/common/ad_cmos_clk.v" \ + "$ad_hdl_dir/library/common/ad_cmos_in.v" \ + "$ad_hdl_dir/library/common/ad_cmos_out.v" \ "$ad_hdl_dir/library/common/ad_mul.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_dds_sine.v" \ @@ -32,6 +35,7 @@ adi_ip_files axi_ad9361 [list \ "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ "axi_ad9361_constr.xdc" \ "axi_ad9361_dev_if.v" \ + "axi_ad9361_cmos_if.v" \ "axi_ad9361_rx_pnmon.v" \ "axi_ad9361_rx_channel.v" \ "axi_ad9361_rx.v" \ @@ -46,11 +50,36 @@ adi_ip_constraints axi_ad9361 [list \ "axi_ad9361_constr.xdc" \ "$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ] +set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \ + [ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \ + [ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out -of_objects [ipx::current_core]] + ipx::remove_bus_interface rst [ipx::current_core] ipx::remove_bus_interface clk [ipx::current_core] ipx::remove_bus_interface l_clk [ipx::current_core] diff --git a/library/axi_ad9361/axi_ad9361_rx.v b/library/axi_ad9361/axi_ad9361_rx.v index e28ee0978..22a699616 100644 --- a/library/axi_ad9361/axi_ad9361_rx.v +++ b/library/axi_ad9361/axi_ad9361_rx.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // ADC channel-need to work on dual mode for pn sequence `timescale 1ns/100ps @@ -115,9 +113,9 @@ module axi_ad9361_rx ( // delay interface - output [ 6:0] up_dld; - output [34:0] up_dwdata; - input [34:0] up_drdata; + output [12:0] up_dld; + output [64:0] up_dwdata; + input [64:0] up_drdata; input delay_clk; output delay_rst; input delay_locked; @@ -377,7 +375,7 @@ module axi_ad9361_rx ( // adc delay control - up_delay_cntrl #(.DATA_WIDTH(7), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked), diff --git a/library/axi_ad9361/axi_ad9361_tx.v b/library/axi_ad9361/axi_ad9361_tx.v index 6c36e28b6..2b788d476 100644 --- a/library/axi_ad9361/axi_ad9361_tx.v +++ b/library/axi_ad9361/axi_ad9361_tx.v @@ -111,9 +111,9 @@ module axi_ad9361_tx ( // delay interface - output [ 9:0] up_dld; - output [49:0] up_dwdata; - input [49:0] up_drdata; + output [15:0] up_dld; + output [79:0] up_dwdata; + input [79:0] up_drdata; input delay_clk; output delay_rst; input delay_locked; @@ -387,7 +387,7 @@ module axi_ad9361_tx ( // dac delay control - up_delay_cntrl #(.DATA_WIDTH(10), .BASE_ADDRESS(6'h12)) i_delay_cntrl ( + up_delay_cntrl #(.DATA_WIDTH(16), .BASE_ADDRESS(6'h12)) i_delay_cntrl ( .delay_clk (delay_clk), .delay_rst (delay_rst), .delay_locked (delay_locked),