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zc706-plddr3: read changes to lower dma clock

main
Rejeesh Kutty 2014-06-25 09:20:14 -04:00
parent 4877df9bec
commit 57bb3705f2
3 changed files with 38 additions and 17 deletions
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4
projects/common/zc706/zc706_system_mig.prj
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@ -23,8 +23,8 @@
<VccAuxIO>2.0V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<UIExtraClocks>1</UIExtraClocks>
<MMCMClkOut0> 6.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>

48
projects/common/zc706/zc706_system_plddr3.tcl
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@ -53,10 +53,11 @@ proc p_plddr3_fifo {p_name m_name m_width} {
set_property -dict [list CONFIG.Output_Data_Width {64}] $rfifo_mem
set_property -dict [list CONFIG.Overflow_Flag {true}] $rfifo_mem
set_property -dict [list CONFIG.Programmable_Full_Type {Single_Programmable_Full_Threshold_Constant}] $rfifo_mem
set_property -dict [list CONFIG.Full_Threshold_Assert_Value {1000}] $rfifo_mem
set_property -dict [list CONFIG.Full_Threshold_Assert_Value {800}] $rfifo_mem
set axi_fifo2s [create_bd_cell -type ip -vlnv analog.com:user:axi_fifo2s:1.0 axi_fifo2s]
set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_fifo2s
set_property -dict [list CONFIG.AXI_ADDRLIMIT {0xa0000000}] $axi_fifo2s
set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_fifo2s
set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_fifo2s
set_property -dict [list CONFIG.DATA_WIDTH {512}] $axi_fifo2s
@ -86,25 +87,31 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net dma_rstn [get_bd_pins axi_fifo2s/axi_resetn]
connect_bd_net -net dma_rstn [get_bd_pins rfifo_ctl/rstn]
connect_bd_net -net dma_rstn [get_bd_pins wfifo_ctl/rstn]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_fifo2s/axi_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_fifo2s/m_clk]
connect_bd_net -net dma_clk [get_bd_pins wfifo_ctl/s_clk]
connect_bd_net -net dma_clk [get_bd_pins wfifo_mem/rd_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/m_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_ddr_cntrl/ui_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/axi_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/m_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_ctl/s_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_mem/rd_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_ctl/m_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_mem/wr_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/s_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/rd_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/wr_clk]
connect_bd_net -net dma_clk [get_bd_pins dma_clk]
connect_bd_net -net dma_wr [get_bd_pins dma_wr] [get_bd_pins rfifo_ctl/s_wr]
connect_bd_net -net dma_wdata [get_bd_pins dma_wdata] [get_bd_pins rfifo_ctl/s_wdata]
connect_bd_net -net dma_wovf [get_bd_pins dma_wovf] [get_bd_pins rfifo_ctl/s_wovf]
connect_bd_net -net wfifo_ctl_fifo_rst [get_bd_pins wfifo_ctl/fifo_rst] [get_bd_pins wfifo_mem/rst]
connect_bd_net -net wfifo_ctl_fifo_wr [get_bd_pins wfifo_ctl/fifo_wr] [get_bd_pins wfifo_mem/wr_en]
connect_bd_net -net wfifo_ctl_fifo_wdata [get_bd_pins wfifo_ctl/fifo_wdata] [get_bd_pins wfifo_mem/din]
connect_bd_net -net wfifo_ctl_fifo_wfull [get_bd_pins wfifo_ctl/fifo_wfull] [get_bd_pins wfifo_mem/full]
connect_bd_net -net wfifo_ctl_fifo_wovf [get_bd_pins wfifo_ctl/fifo_wovf] [get_bd_pins wfifo_mem/overflow]
connect_bd_net -net dma_wr [get_bd_pins dma_wr] [get_bd_pins rfifo_ctl/s_wr]
connect_bd_net -net dma_wdata [get_bd_pins dma_wdata] [get_bd_pins rfifo_ctl/s_wdata]
connect_bd_net -net dma_wovf [get_bd_pins dma_wovf] [get_bd_pins rfifo_ctl/s_wovf]
connect_bd_net -net rfifo_ctl_fifo_rd [get_bd_pins rfifo_ctl/fifo_rd] [get_bd_pins rfifo_mem/rd_en]
connect_bd_net -net rfifo_ctl_fifo_rdata [get_bd_pins rfifo_ctl/fifo_rdata] [get_bd_pins rfifo_mem/dout]
connect_bd_net -net rfifo_ctl_fifo_rempty [get_bd_pins rfifo_ctl/fifo_rempty] [get_bd_pins rfifo_mem/empty]
connect_bd_net -net wfifo_ctl_fifo_rd [get_bd_pins wfifo_ctl/fifo_rd] [get_bd_pins wfifo_mem/rd_en]
connect_bd_net -net wfifo_ctl_fifo_rdata [get_bd_pins wfifo_ctl/fifo_rdata] [get_bd_pins wfifo_mem/dout]
connect_bd_net -net wfifo_ctl_fifo_rempty [get_bd_pins wfifo_ctl/fifo_rempty] [get_bd_pins wfifo_mem/empty]
@ -113,9 +120,6 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net rfifo_ctl_fifo_wdata [get_bd_pins rfifo_ctl/fifo_wdata] [get_bd_pins rfifo_mem/din]
connect_bd_net -net rfifo_ctl_fifo_wfull [get_bd_pins rfifo_ctl/fifo_wfull] [get_bd_pins rfifo_mem/full]
connect_bd_net -net rfifo_ctl_fifo_wovf [get_bd_pins rfifo_ctl/fifo_wovf] [get_bd_pins rfifo_mem/overflow]
connect_bd_net -net rfifo_ctl_fifo_rd [get_bd_pins rfifo_ctl/fifo_rd] [get_bd_pins rfifo_mem/rd_en]
connect_bd_net -net rfifo_ctl_fifo_rdata [get_bd_pins rfifo_ctl/fifo_rdata] [get_bd_pins rfifo_mem/dout]
connect_bd_net -net rfifo_ctl_fifo_rempty [get_bd_pins rfifo_ctl/fifo_rempty] [get_bd_pins rfifo_mem/empty]
connect_bd_net -net axi_fifo2s_swr [get_bd_pins axi_fifo2s/m_wr] [get_bd_pins wfifo_ctl/s_wr]
connect_bd_net -net axi_fifo2s_swdata [get_bd_pins axi_fifo2s/m_wdata] [get_bd_pins wfifo_ctl/s_wdata]
connect_bd_net -net axi_fifo2s_swovf [get_bd_pins axi_fifo2s/m_wovf] [get_bd_pins wfifo_ctl/s_wovf]
@ -123,7 +127,21 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net axi_fifo2s_axi_mwdata [get_bd_pins axi_fifo2s/axi_mwdata] [get_bd_pins rfifo_ctl/m_wdata]
connect_bd_net -net axi_fifo2s_axi_mwovf [get_bd_pins axi_fifo2s/axi_mwovf] [get_bd_pins rfifo_ctl/m_wovf]
connect_bd_net -net axi_fifo2s_axi_mwpfull [get_bd_pins axi_fifo2s/axi_mwpfull] [get_bd_pins rfifo_mem/prog_full]
set ila_ddr_mon_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_ddr_mon_1]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ddr_mon_1
set_property -dict [list CONFIG.C_PROBE0_WIDTH {18}] $ila_ddr_mon_1
connect_bd_net [get_bd_pins axi_fifo2s/dbg_adc_clk] [get_bd_pins ila_ddr_mon_1/clk]
connect_bd_net [get_bd_pins axi_fifo2s/dbg_adc_data] [get_bd_pins ila_ddr_mon_1/probe0]
set ila_ddr_mon_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_ddr_mon_2]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {1}] $ila_ddr_mon_2
set_property -dict [list CONFIG.C_PROBE0_WIDTH {166}] $ila_ddr_mon_2
connect_bd_net [get_bd_pins axi_fifo2s/dbg_axi_clk] [get_bd_pins ila_ddr_mon_2/clk]
connect_bd_net [get_bd_pins axi_fifo2s/dbg_axi_data] [get_bd_pins ila_ddr_mon_2/probe0]
current_bd_instance $c_instance
}

3
projects/scripts/adi_project.tcl
View File

@ -96,6 +96,9 @@ proc adi_project_create {project_name} {
create_bd_design "system"
source system_bd.tcl
save_bd_design
validate_bd_design
generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
make_wrapper -files [get_files $project_system_dir/system.bd] -top
import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v