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axi_dacfifo: Add bypass logic

main
Istvan Csomortani 2016-05-17 11:04:21 +03:00
parent f10c1e6e93
commit 578376c8fe
2 changed files with 15 additions and 2 deletions
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15
library/axi_dacfifo/axi_dacfifo.v
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@ -60,6 +60,8 @@ module axi_dacfifo (
dac_dovf,
dac_xfer_out,
dac_fifo_bypass,
// axi interface
axi_clk,
@ -139,6 +141,8 @@ module axi_dacfifo (
output dac_dovf;
output dac_xfer_out;
input dac_fifo_bypass;
// axi interface
input axi_clk;
@ -209,6 +213,8 @@ module axi_dacfifo (
dma_dacrst_m2 <= dma_dacrst_m1;
end
assign dma_rst_s = dma_dacrst_m2;
wire [(DAC_DATA_WIDTH-1):0] dac_data_s;
wire dma_ready_s;
// instantiations
@ -223,7 +229,7 @@ module axi_dacfifo (
.dma_clk (dma_clk),
.dma_rst (dma_rst_s),
.dma_data (dma_data),
.dma_ready (dma_ready),
.dma_ready (dma_ready_s),
.dma_valid (dma_valid),
.dma_xfer_req (dma_xfer_req),
.dma_xfer_last (dma_xfer_last),
@ -301,10 +307,15 @@ module axi_dacfifo (
.axi_xfer_req (axi_xfer_req_s),
.dac_clk (dac_clk),
.dac_valid (dac_valid),
.dac_data (dac_data),
.dac_data (dac_data_s),
.dac_xfer_out (dac_xfer_out),
.dac_dunf (dac_dunf),
.dac_dovf (dac_dovf));
// output logic
assign dac_data = (dac_fifo_bypass) ? dma_data : dac_data_s;
assign dma_ready = (dac_fifo_bypass) ? dac_valid : dma_ready_s;
endmodule

2
projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
View File

@ -25,6 +25,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
create_bd_pin -dir O dac_dunf
create_bd_pin -dir O dac_dovf
create_bd_pin -dir O dac_xfer_out
create_bd_pin -dir I dac_fifo_bypass
create_bd_pin -dir I -type clk dma_clk
create_bd_pin -dir I dma_rvalid
@ -80,6 +81,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
ad_connect dma_xfer_req axi_dacfifo/dma_xfer_req
ad_connect dma_xfer_last axi_dacfifo/dma_xfer_last
ad_connect dac_fifo_bypass axi_dacfifo/dac_fifo_bypass
ad_connect dac_valid axi_dacfifo/dac_valid
ad_connect dac_data axi_dacfifo/dac_data
ad_connect dac_dunf axi_dacfifo/dac_dunf