daq1: clean up dma interfaces
Rejeesh Kutty
parent
7c98a783c5
commit
577441bd0c
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@ -15,6 +15,16 @@ set rx_sysref [create_bd_port -dir I rx_sysref]
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set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p]
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set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n]
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set dac_clk [create_bd_port -dir O dac_clk]
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set dac_valid_0 [create_bd_port -dir O dac_valid_0]
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set dac_enable_0 [create_bd_port -dir O dac_enable_0]
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set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0]
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set dac_valid_1 [create_bd_port -dir O dac_valid_1]
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set dac_enable_1 [create_bd_port -dir O dac_enable_1]
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set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1]
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set dac_drd [create_bd_port -dir I dac_drd]
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set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata]
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set adc_clk [create_bd_port -dir O adc_clk]
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set adc_enable_a [create_bd_port -dir O adc_enable_a]
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set adc_valid_a [create_bd_port -dir O adc_valid_a]
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@ -22,9 +32,9 @@ set adc_data_a [create_bd_port -dir O -from 31 -to 0 adc_data_a]
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set adc_enable_b [create_bd_port -dir O adc_enable_b]
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set adc_valid_b [create_bd_port -dir O adc_valid_b]
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set adc_data_b [create_bd_port -dir O -from 31 -to 0 adc_data_b]
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set dma_wr [create_bd_port -dir I dma_wr]
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set dma_sync [create_bd_port -dir I dma_sync]
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set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data]
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set adc_dwr [create_bd_port -dir I adc_dwr]
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set adc_dsync [create_bd_port -dir I adc_dsync]
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set adc_ddata [create_bd_port -dir I -from 63 -to 0 adc_ddata]
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set tx_ref_clk_p [create_bd_port -dir I tx_ref_clk_p]
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set tx_ref_clk_n [create_bd_port -dir I tx_ref_clk_n]
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@ -136,6 +146,7 @@ connect_bd_net -net axi_daq1_gt_rx_sync [get_bd_pins axi_daq1_gt/rx_sy
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connect_bd_net -net axi_daq1_gt_rx_ext_sysref [get_bd_pins axi_daq1_gt/rx_ext_sysref] [get_bd_ports rx_sysref]
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# connections (adc)
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk_g]
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk]
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connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_ad9250_core/rx_clk]
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@ -160,11 +171,14 @@ connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/a
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connect_bd_net -net axi_ad9250_adc_enable_b [get_bd_pins axi_ad9250_core/adc_enable_b] [get_bd_ports adc_enable_b]
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connect_bd_net -net axi_ad9250_adc_valid_b [get_bd_pins axi_ad9250_core/adc_valid_b] [get_bd_ports adc_valid_b]
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connect_bd_net -net axi_ad9250_adc_data_b [get_bd_pins axi_ad9250_core/adc_data_b] [get_bd_ports adc_data_b]
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connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports dma_wr]
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connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports dma_sync]
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connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports dma_data]
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connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/adc_dovf] [get_bd_pins axi_ad9250_dma/fifo_wr_overflow]
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connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr]
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connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync]
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connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata]
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connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2]
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connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk]
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# connections (dac)
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connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_pins axi_ad9122_core/dac_clk_in_p] [get_bd_ports tx_ref_clk_p]
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@ -176,11 +190,19 @@ connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_pins axi_ad9122_core/d
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connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_pins axi_ad9122_core/dac_data_out_p] [get_bd_ports tx_data_p]
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connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_pins axi_ad9122_core/dac_data_out_n] [get_bd_ports tx_data_n]
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connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_pins axi_ad9122_core/dac_div_clk] [get_bd_pins axi_ad9122_dma/fifo_rd_clk]
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connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122_core/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en]
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connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122_core/dac_ddata] [get_bd_pins axi_ad9122_dma/fifo_rd_dout]
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connect_bd_net -net axi_ad9122_dac_valid_0 [get_bd_pins axi_ad9122_core/dac_valid_0] [get_bd_ports dac_valid_0]
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connect_bd_net -net axi_ad9122_dac_enable_0 [get_bd_pins axi_ad9122_core/dac_enable_0] [get_bd_ports dac_enable_0]
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connect_bd_net -net axi_ad9122_dac_ddata_0 [get_bd_pins axi_ad9122_core/dac_ddata_0] [get_bd_ports dac_ddata_0]
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connect_bd_net -net axi_ad9122_dac_valid_1 [get_bd_pins axi_ad9122_core/dac_valid_1] [get_bd_ports dac_valid_1]
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connect_bd_net -net axi_ad9122_dac_enable_1 [get_bd_pins axi_ad9122_core/dac_enable_1] [get_bd_ports dac_enable_1]
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connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/dac_ddata_1] [get_bd_ports dac_ddata_1]
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connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd]
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connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata]
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connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow]
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connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3]
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connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk]
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# interconnect (cpu)
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connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi]
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@ -266,6 +288,7 @@ connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9250_dma/m_dest_axi_ar
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# ila
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set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {9} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {170} ] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {4} ] $ila_jesd_rx_mon
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@ -180,57 +180,94 @@ module system_top (
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inout spi_sdio;
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// internal registers
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reg dma_wr = 'd0;
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reg [63:0] dma_data = 'd0;
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reg dac_drd = 'd0;
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reg [63:0] dac_ddata_0 = 'd0;
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reg [63:0] dac_ddata_1 = 'd0;
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reg adc_dwr = 'd0;
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reg [63:0] adc_ddata = 'd0;
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// internal signals
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wire [39:0] gpio_i;
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wire [39:0] gpio_o;
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wire [39:0] gpio_t;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire [ 2:0] spi_csn;
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wire adc_clk;
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wire adc_enable_a;
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wire [31:0] adc_data_a;
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wire adc_enable_b;
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wire [31:0] adc_data_b;
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wire adc_enable_a;
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wire adc_enable_b;
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wire dac_clk;
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wire [127:0] dac_ddata;
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wire dac_enable_0;
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wire dac_enable_1;
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// pack & unpack data
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always @(posedge dac_clk) begin
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case ({dac_enable_1, dac_enable_0})
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2'b11: begin
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dac_drd <= 1'b1;
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dac_ddata_1[63:48] <= dac_ddata[127:112];
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dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
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dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
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dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
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dac_ddata_0[63:48] <= dac_ddata[111: 96];
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dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
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dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
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dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
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end
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2'b01: begin
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dac_drd <= ~dac_drd;
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dac_ddata_1 <= 64'd0;
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dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
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end
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2'b10: begin
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dac_drd <= ~dac_drd;
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dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
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dac_ddata_0 <= 64'd0;
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end
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default: begin
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dac_drd <= 1'b0;
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dac_ddata_1 <= 64'd0;
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dac_ddata_0 <= 64'd0;
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end
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endcase
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end
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always @(posedge adc_clk) begin
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case ({adc_enable_b, adc_enable_a})
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2'b11: begin
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dma_wr <= 1'b1;
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dma_data[63:48] <= adc_data_b[31:16];
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dma_data[47:32] <= adc_data_a[31:16];
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dma_data[31:16] <= adc_data_b[15: 0];
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dma_data[15: 0] <= adc_data_a[15: 0];
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adc_dwr <= 1'b1;
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adc_ddata[63:48] <= adc_data_b[31:16];
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adc_ddata[47:32] <= adc_data_a[31:16];
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adc_ddata[31:16] <= adc_data_b[15: 0];
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adc_ddata[15: 0] <= adc_data_a[15: 0];
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end
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2'b10: begin
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dma_wr <= ~dma_wr;
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dma_data[63:48] <= adc_data_b[31:16];
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dma_data[47:32] <= adc_data_b[15: 0];
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dma_data[31:16] <= dma_data[63:48];
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dma_data[15: 0] <= dma_data[47:32];
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adc_dwr <= ~adc_dwr;
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adc_ddata[63:48] <= adc_data_b[31:16];
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adc_ddata[47:32] <= adc_data_b[15: 0];
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adc_ddata[31:16] <= adc_ddata[63:48];
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adc_ddata[15: 0] <= adc_ddata[47:32];
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end
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2'b01: begin
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dma_wr <= ~dma_wr;
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dma_data[63:48] <= adc_data_a[31:16];
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dma_data[47:32] <= adc_data_a[15: 0];
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dma_data[31:16] <= dma_data[63:48];
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dma_data[15: 0] <= dma_data[47:32];
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adc_dwr <= ~adc_dwr;
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adc_ddata[63:48] <= adc_data_a[31:16];
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adc_ddata[47:32] <= adc_data_a[15: 0];
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adc_ddata[31:16] <= adc_ddata[63:48];
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adc_ddata[15: 0] <= adc_ddata[47:32];
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end
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default: begin
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dma_wr <= 1'b0;
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dma_data[63:48] <= 16'd0;
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dma_data[47:32] <= 16'd0;
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dma_data[31:16] <= 16'd0;
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dma_data[15: 0] <= 16'd0;
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adc_dwr <= 1'b0;
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adc_ddata[63:48] <= 16'd0;
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adc_ddata[47:32] <= 16'd0;
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adc_ddata[31:16] <= 16'd0;
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adc_ddata[15: 0] <= 16'd0;
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end
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endcase
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end
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@ -305,6 +342,25 @@ module system_top (
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.adc_clk (adc_clk),
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.adc_data_a (adc_data_a),
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.adc_data_b (adc_data_b),
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.adc_ddata (adc_ddata),
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.adc_dsync (1'b1),
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.adc_dwr (adc_dwr),
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.adc_enable_a (adc_enable_a),
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.adc_enable_b (adc_enable_b),
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.adc_valid_a (),
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.adc_valid_b (),
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.dac_clk (dac_clk),
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.dac_ddata (dac_ddata),
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.dac_ddata_0 (dac_ddata_0),
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.dac_ddata_1 (dac_ddata_1),
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.dac_drd (dac_drd),
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.dac_enable_0 (dac_enable_0),
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.dac_enable_1 (dac_enable_1),
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.dac_valid_0 (),
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.dac_valid_1 (),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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@ -317,16 +373,6 @@ module system_top (
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.rx_ref_clk (rx_ref_clk),
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.rx_sync (rx_sync),
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.rx_sysref (rx_sysref),
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.adc_clk (adc_clk),
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.adc_data_a (adc_data_a),
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.adc_data_b (adc_data_b),
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.adc_enable_a (adc_enable_a),
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.adc_enable_b (adc_enable_b),
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.adc_valid_a (),
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.adc_valid_b (),
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.dma_data (dma_data),
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.dma_sync (1'b1),
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.dma_wr (dma_wr),
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.spdif (spdif),
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.spi_clk_i (spi_clk),
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.spi_clk_o (spi_clk),
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