From 56a65b717c3bb3262150334fe7a7ba9cfc035226 Mon Sep 17 00:00:00 2001
From: Benjamin Menkuec <benjamin@menkuec.de>
Date: Tue, 17 May 2022 13:46:30 +0200
Subject: [PATCH] mark axi_gpreg.v as systemverilog, otherwise it gives an
 error with vivado 2022.1

---
 library/axi_gpreg/axi_gpreg_ip.tcl | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/library/axi_gpreg/axi_gpreg_ip.tcl b/library/axi_gpreg/axi_gpreg_ip.tcl
index 85a78377b..02c9085fc 100644
--- a/library/axi_gpreg/axi_gpreg_ip.tcl
+++ b/library/axi_gpreg/axi_gpreg_ip.tcl
@@ -13,6 +13,8 @@ adi_ip_files axi_gpreg [list \
   "axi_gpreg_constr.ttcl" \
   "axi_gpreg_clock_mon.v" \
   "axi_gpreg.v" ]
+  
+set_property FILE_TYPE SystemVerilog [get_files "axi_gpreg.v"]
 
 adi_ip_properties axi_gpreg
 adi_ip_ttcl axi_gpreg "axi_gpreg_constr.ttcl"