From 568f2e180f92fa19cfd5d1c1888b369d90d99768 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 3 Apr 2018 14:09:47 +0300 Subject: [PATCH] ad_mul.v: Add parameters for A and B input widths The out width will be A + B. This change is backward compatible and it applies to both Altera and Xilinx. --- library/altera/common/ad_mul.v | 16 +++++++++------- library/xilinx/common/ad_mul.v | 14 ++++++++------ 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/library/altera/common/ad_mul.v b/library/altera/common/ad_mul.v index cb3458713..eaaef8b79 100644 --- a/library/altera/common/ad_mul.v +++ b/library/altera/common/ad_mul.v @@ -37,14 +37,16 @@ module ad_mul #( + parameter A_DATA_WIDTH = 17, + parameter B_DATA_WIDTH = 17, parameter DELAY_DATA_WIDTH = 16) ( // data_p = data_a * data_b; - input clk, - input [16:0] data_a, - input [16:0] data_b, - output [33:0] data_p, + input clk, + input [ A_DATA_WIDTH-1:0] data_a, + input [ B_DATA_WIDTH-1:0] data_b, + output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p, // delay interface @@ -67,9 +69,9 @@ module ad_mul #( lpm_mult #( .lpm_type ("lpm_mult"), - .lpm_widtha (17), - .lpm_widthb (17), - .lpm_widthp (34), + .lpm_widtha (A_DATA_WIDTH), + .lpm_widthb (B_DATA_WIDTH), + .lpm_widthp (A_DATA_WIDTH + B_DATA_WIDTH), .lpm_representation ("SIGNED"), .lpm_pipeline (3)) i_lpm_mult ( diff --git a/library/xilinx/common/ad_mul.v b/library/xilinx/common/ad_mul.v index 195c3da84..9b64ebccc 100644 --- a/library/xilinx/common/ad_mul.v +++ b/library/xilinx/common/ad_mul.v @@ -37,14 +37,16 @@ module ad_mul #( + parameter A_DATA_WIDTH = 17, + parameter B_DATA_WIDTH = 17, parameter DELAY_DATA_WIDTH = 16) ( // data_p = data_a * data_b; - input clk, - input [16:0] data_a, - input [16:0] data_b, - output [33:0] data_p, + input clk, + input [ A_DATA_WIDTH-1:0] data_a, + input [ B_DATA_WIDTH-1:0] data_b, + output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p, // delay interface @@ -67,8 +69,8 @@ module ad_mul #( MULT_MACRO #( .LATENCY (3), - .WIDTH_A (17), - .WIDTH_B (17)) + .WIDTH_A (A_DATA_WIDTH), + .WIDTH_B (B_DATA_WIDTH)) i_mult_macro ( .CE (1'b1), .RST (1'b0),