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axi_adcfifo: Add missing constraints 

Add missing timing exceptions on paths between the DMA and DDR clock
domains. All these paths are properly synchronized using CDC in the HDL,
but are missing timing exceptions in the XDC file. This can lead to timing
errors when building a design using the axi_adc_fifo.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-09-13 11:31:07 +02:00
parent cafa811c74
commit 55daa786fa
1 changed files with 7 additions and 1 deletions
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8
library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc
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@ -3,6 +3,7 @@ set_property ASYNC_REG TRUE \
[get_cells -hier *axi_waddr_m1_reg*] \
[get_cells -hier *axi_waddr_m2_reg*] \
[get_cells -hier *adc_xfer_req_m_reg[0]*]
[get_cells -hier *axi_xfer_req_m_reg[0]*]
set_false_path -from [get_cells *dma_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_*_m* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
@ -20,7 +21,12 @@ set_false_path -from [get_cells *up_xfer_* -hierarchical -filter {PRIMITIVE_SUBG
-to [get_cells *d_xfer_* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *adc_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_rel_waddr* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *axi_waddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *dma_waddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path -from [get_cells *dma_raddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}] \
-to [get_cells *axi_raddr_rel_reg* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path \
-to [get_cells *adc_xfer_req_m_reg[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]
set_false_path \
-to [get_cells *axi_xfer_req_m_reg[0]* -hierarchical -filter {PRIMITIVE_SUBGROUP == flop}]