library/common/ad_dds: Fix indentation
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@ -118,21 +118,21 @@ module ad_dds #(
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// phase accumulator
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for (i=1; i <= CLK_RATIO; i=i+1) begin: dds_phase
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always @(posedge clk) begin
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if (dac_data_sync == 1'b1) begin
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dac_dds_phase_0[i] <= 'd0;
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dac_dds_phase_1[i] <= 'd0;
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end else if (sync_min_pulse_m[1] == 1'b1) begin
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if (i == 1) begin
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dac_dds_phase_0[1] <= tone_1_init_offset;
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dac_dds_phase_1[1] <= tone_2_init_offset;
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end else if (CLK_RATIO > 1)begin
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dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word;
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dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word;
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end
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end else if (dac_valid == 1'b1) begin
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dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0;
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dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1;
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if (dac_data_sync == 1'b1) begin
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dac_dds_phase_0[i] <= 'd0;
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dac_dds_phase_1[i] <= 'd0;
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end else if (sync_min_pulse_m[1] == 1'b1) begin
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if (i == 1) begin
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dac_dds_phase_0[1] <= tone_1_init_offset;
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dac_dds_phase_1[1] <= tone_2_init_offset;
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end else if (CLK_RATIO > 1)begin
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dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word;
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dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word;
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end
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end else if (dac_valid == 1'b1) begin
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dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0;
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dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1;
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end
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end
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// phase to amplitude convertor
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