diff --git a/library/xilinx/axi_xcvrlb/Makefile b/library/xilinx/axi_xcvrlb/Makefile new file mode 100644 index 000000000..34d8a9662 --- /dev/null +++ b/library/xilinx/axi_xcvrlb/Makefile @@ -0,0 +1,57 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := axi_adxcvr_ip.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip.tcl +M_DEPS += ../../common/up_axi.v +M_DEPS += axi_adxcvr_es.v +M_DEPS += axi_adxcvr_up.v +M_DEPS += axi_adxcvr_mdrp.v +M_DEPS += axi_adxcvr_mstatus.v +M_DEPS += axi_adxcvr.v +M_DEPS += ../../interfaces/if_xcvr_cm.xml +M_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml +M_DEPS += ../../interfaces/if_xcvr_ch.xml +M_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all dep clean clean-all +all: dep axi_adxcvr.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +axi_adxcvr.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) axi_adxcvr_ip.tcl >> axi_adxcvr_ip.log 2>&1 + +dep: + make -C ../../interfaces +#################################################################################### +#################################################################################### diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v new file mode 100644 index 000000000..5c10c5572 --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb.v @@ -0,0 +1,200 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_xcvrlb #( + + // parameters + + parameter NUM_OF_LANES = 1) ( + + // transceiver interface + + input ref_clk, + input [(NUM_OF_LANES-1):0] rx_p, + input [(NUM_OF_LANES-1):0] rx_n, + output [(NUM_OF_LANES-1):0] tx_p, + output [(NUM_OF_LANES-1):0] tx_n, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [31:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [31:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready); + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [31:0] up_status = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal signals + + wire up_rstn; + wire up_clk; + wire up_wreq_s; + wire [ 7:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [ 7:0] up_raddr_s; + wire [31:0] up_status_s; + + // defaults + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + assign up_status_s[31:NUM_OF_LANES] = 'd0; + + // register access + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_resetn <= 'd0; + up_status <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin + up_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin + up_status <= up_status_s | (up_status & ~up_wdata); + end else begin + up_status <= up_status_s | up_status; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s) + 10'h000: up_rdata <= VERSION; + 10'h001: up_rdata <= ID; + 10'h002: up_rdata <= up_scratch; + 10'h004: up_rdata <= {31'd0, up_resetn}; + 10'h005: up_rdata <= up_status; + default: up_rdata <= 32'd0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // instantiations + + genvar n; + generate + for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes + axi_xcvrlb_1 i_xcvrlb_1 ( + .ref_clk (ref_clk), + .rx_p (rx_p[n]), + .rx_n (rx_n[n]), + .tx_p (tx_p[n]), + .tx_n (tx_n[n]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_resetn (up_resetn), + .up_status (up_status_s[n])); + end + endgenerate + + up_axi #(.ADDRESS_WIDTH (8)) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v new file mode 100644 index 000000000..610ef3b5f --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v @@ -0,0 +1,321 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_xcvrlb_1 ( + + // transceiver interface + + input ref_clk, + input rx_p, + input rx_n, + output tx_p, + output tx_n, + + // processor interface + + input up_rstn, + input up_clk, + input up_resetn, + output up_status); + + // internal registers + + reg [ 3:0] rx_kcount = 'd0; + reg rx_calign = 'd0; + reg [31:0] rx_data = 'd0; + reg [31:0] rx_pn_data = 'd0; + reg [ 3:0] tx_charisk = 'd0; + reg [31:0] tx_data = 'd0; + reg [31:0] tx_pn_data = 'd0; + reg [ 3:0] up_pll_rst_cnt = 'd0; + reg [ 3:0] up_rst_cnt = 'd0; + reg [ 6:0] up_user_ready_cnt = 'd0; + reg up_status_int = 'd1; + + // internal signals + + wire rx_status_s; + wire [31:0] rx_pn_data_s; + wire rx_pn_oos_s; + wire rx_pn_err_s; + wire [ 3:0] rx_charisk_s; + wire [ 7:0] rx_error_s; + wire [31:0] rx_data_s; + wire up_pll_rst_s; + wire up_rst_s; + wire up_user_ready_s; + wire up_pll_locked_s; + wire up_rst_done_s; + wire up_pn_oos_s; + wire up_pn_err_s; + wire up_rx_pll_locked_s; + wire up_rx_rst_done_s; + wire up_tx_pll_locked_s; + wire up_tx_rst_done_s; + + // pn31 function + + function [31:0] pn31; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[31] ^ din[28]; + dout[30] = din[30] ^ din[27]; + dout[29] = din[29] ^ din[26]; + dout[28] = din[28] ^ din[25]; + dout[27] = din[27] ^ din[24]; + dout[26] = din[26] ^ din[23]; + dout[25] = din[25] ^ din[22]; + dout[24] = din[24] ^ din[21]; + dout[23] = din[23] ^ din[20]; + dout[22] = din[22] ^ din[19]; + dout[21] = din[21] ^ din[18]; + dout[20] = din[20] ^ din[17]; + dout[19] = din[19] ^ din[16]; + dout[18] = din[18] ^ din[15]; + dout[17] = din[17] ^ din[14]; + dout[16] = din[16] ^ din[13]; + dout[15] = din[15] ^ din[12]; + dout[14] = din[14] ^ din[11]; + dout[13] = din[13] ^ din[10]; + dout[12] = din[12] ^ din[ 9]; + dout[11] = din[11] ^ din[ 8]; + dout[10] = din[10] ^ din[ 7]; + dout[ 9] = din[ 9] ^ din[ 6]; + dout[ 8] = din[ 8] ^ din[ 5]; + dout[ 7] = din[ 7] ^ din[ 4]; + dout[ 6] = din[ 6] ^ din[ 3]; + dout[ 5] = din[ 5] ^ din[ 2]; + dout[ 4] = din[ 4] ^ din[ 1]; + dout[ 3] = din[ 3] ^ din[ 0]; + dout[ 2] = din[ 2] ^ din[31] ^ din[28]; + dout[ 1] = din[ 1] ^ din[30] ^ din[27]; + dout[ 0] = din[ 0] ^ din[29] ^ din[26]; + pn31 = dout; + end + endfunction + + // receive + + assign rx_status_s = ~(| rx_error_s); + assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data_s : rx_pn_data; + + always @(posedge clk) begin + if (rx_status_s == 1'b0) begin + rx_kcount <= 4'd0; + rx_calign <= 1'd1; + end else if ((rx_charisk_s == 4'hf) && (rx_data_s == {4{8'hbc}})) begin + rx_kcount <= rx_kcount + 1'b1; + if (rx_kcount == 4'hf) begin + rx_calign <= 1'd0; + end + end + end + + always @(posedge clk) begin + if (rx_status_s == 1'b1) begin + rx_data[31:24] = rx_data_s[ 7: 0]; + rx_data[23:16] = rx_data_s[15: 8]; + rx_data[15: 8] = rx_data_s[23:16]; + rx_data[ 7: 0] = rx_data_s[31:24]; + end else begin + rx_data[31:24] = 8'hff; + rx_data[23:16] = 8'hff; + rx_data[15: 8] = 8'hff; + rx_data[ 7: 0] = 8'hff; + end + rx_pn_data <= pn31(rx_pn_data_s); + end + + // transmit + + always @(posedge clk) begin + if (rx_calign == 1'b0) begin + tx_charisk <= 1'd0; + tx_data[31:24] <= tx_pn_data[ 7: 0]; + tx_data[23:16] <= tx_pn_data[15: 8]; + tx_data[15: 8] <= tx_pn_data[23:16]; + tx_data[ 7: 0] <= tx_pn_data[31:24]; + tx_pn_data <= pn31(tx_pn_data); + end else begin + tx_charisk <= 1'd1; + tx_data[31:24] <= 8'hbc; + tx_data[23:16] <= 8'hbc; + tx_data[15: 8] <= 8'hbc; + tx_data[ 7: 0] <= 8'hbc; + tx_pn_data <= {32{1'b1}}; + end + end + + // reset & init + + assign up_status = up_status_int; + assign up_pll_rst_s = up_pll_rst_cnt[3]; + assign up_rst_s = up_rst_cnt[3]; + assign up_user_ready_s = up_user_ready_cnt[6]; + assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s; + assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_pll_rst_cnt <= 4'h8; + up_rst_cnt <= 4'h8; + up_user_ready_cnt <= 7'h00; + up_status_int <= 1'b1; + end else begin + if (up_resetn == 1'b0) begin + up_pll_rst_cnt <= 4'h8; + end else if (up_pll_rst_cnt[3] == 1'b1) begin + up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) || + (up_pll_locked_s == 1'b0)) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin + up_user_ready_cnt <= 7'h00; + end else if (up_user_ready_cnt[6] == 1'b0) begin + up_user_ready_cnt <= up_user_ready_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_done_s == 1'b0)) begin + up_status_int <= 1'b1; + end else begin + up_status_int <= up_pn_oos_s | up_pn_err_s; + end + end + end + + // instantiations + + ad_pnmon #(.DATA_WIDTH(32)) i_pnmon ( + .adc_clk (clk), + .adc_valid_in (1'b1), + .adc_data_in (rx_data), + .adc_data_pn (rx_pn_data), + .adc_pn_oos (rx_pn_oos_s), + .adc_pn_err (rx_pn_err_s)); + + up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_pn_err_s, up_pn_oos_s}), + .d_rst (1'b0), + .d_clk (clk), + .d_data_status ({rx_pn_err_s, rx_pn_oos_s})); + + util_adxcvr_xch #( + .XCVR_ID (15), + .GTH_OR_GTX_N (GTH_OR_GTX_N), + .CPLL_TX_OR_RX_N (0), + .CPLL_FBDIV (2), + .RX_OUT_DIV (1), + .RX_CLK25_DIV (10), + .TX_OUT_DIV (1), + .TX_CLK25_DIV (10), + .PMA_RSV ('h00018480), + .RX_CDR_CFG ('h03000023ff20400020)) + i_xch ( + .qpll2ch_clk (1'b0), + .qpll2ch_ref_clk (1'b0), + .qpll2ch_locked (1'b1), + .cpll_ref_clk (ref_clk), + .rx_p (rx_p), + .rx_n (rx_n), + .rx_out_clk (clk), + .rx_clk (rx_clk), + .rx_charisk (rx_charisk_s), + .rx_disperr (rx_error_s[3:0]), + .rx_notintable (rx_error_s[7:4]), + .rx_data (rx_data_s), + .rx_calign (rx_calign), + .tx_p (tx_p), + .tx_n (tx_n), + .tx_out_clk (), + .tx_clk (clk), + .tx_charisk ({4{tx_charisk}}), + .tx_data (tx_data), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_sel (1'd0), + .up_es_enb (1'd0), + .up_es_addr (12'd0), + .up_es_wr (1'd0), + .up_es_wdata (16'd0), + .up_es_rdata (), + .up_es_ready (), + .up_rx_pll_rst (up_pll_rst_s), + .up_rx_pll_locked (up_rx_pll_locked_s), + .up_rx_rst (up_rst_s), + .up_rx_user_ready (up_user_ready_s), + .up_rx_rst_done (up_rx_rst_done_s), + .up_rx_lpm_dfe_n (1'd0), + .up_rx_rate (3'd0), + .up_rx_sys_clk_sel (2'd0), + .up_rx_out_clk_sel (3'd2), + .up_rx_sel (1'd0), + .up_rx_enb (1'd0), + .up_rx_addr (12'd0), + .up_rx_wr (1'd0), + .up_rx_wdata (16'd0), + .up_rx_rdata (), + .up_rx_ready (), + .up_tx_pll_rst (up_pll_rst_s), + .up_tx_pll_locked (up_tx_pll_locked_s), + .up_tx_rst (up_rst_s), + .up_tx_user_ready (up_user_ready_s), + .up_tx_rst_done (up_tx_rst_done_s), + .up_tx_lpm_dfe_n (1'd0), + .up_tx_rate (3'd0), + .up_tx_sys_clk_sel (2'd0), + .up_tx_out_clk_sel (3'd2), + .up_tx_sel (1'd0), + .up_tx_enb (1'd0), + .up_tx_addr (12'd0), + .up_tx_wr (1'd0), + .up_tx_wdata (16'd0), + .up_tx_rdata (), + .up_tx_ready ()); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl new file mode 100644 index 000000000..c7c179d37 --- /dev/null +++ b/library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl @@ -0,0 +1,58 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_xcvrlb +adi_ip_files axi_xcvrlb [list \ + "$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_xcvrlb_1.v" \ + "axi_xcvrlb.v" ] + +adi_ip_properties_lite axi_xcvrlb + +ipx::remove_all_bus_interface [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +ipx::add_memory_map {s_axi} [ipx::current_core] +set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] +ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] +set_property range {1024} [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + +ipx::save_core [ipx::current_core] +