axi_adxcvr- compile fixes

library/altera/axi_adxcvr/axi_adxcvr.v

@@ -43,8 +43,7 @@ module axi_adxcvr (
 
   output                        up_rst,
   input                         up_ref_pll_locked,
-  input           up_pll_locked,
+  input   [(NUM_OF_LANES-1):0]  up_ready,
-  input           up_ready,
 
   input                         s_axi_clk,
   input                         s_axi_aresetn,
@@ -72,6 +71,7 @@ module axi_adxcvr (
 
   parameter   integer ID = 0;
   parameter   integer TX_OR_RX_N = 0;
+  parameter   integer NUM_OF_LANES = 4;
 
   // internal signals
 
@@ -95,11 +95,11 @@ module axi_adxcvr (
 
   axi_adxcvr_up #(
     .ID (ID),
-    .TX_OR_RX_N (TX_OR_RX_N))
+    .TX_OR_RX_N (TX_OR_RX_N),
+    .NUM_OF_LANES (NUM_OF_LANES))
   i_up (
     .up_rst (up_rst),
     .up_ref_pll_locked (up_ref_pll_locked),
-    .up_pll_locked (up_pll_locked),
     .up_ready (up_ready),
     .up_rstn (up_rstn),
     .up_clk (up_clk),

library/altera/axi_adxcvr/axi_adxcvr_hw.tcl

@@ -5,10 +5,11 @@ source ../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
 
 set_module_property NAME axi_adxcvr
-set_module_property DESCRIPTION "AXI ADXCVR Interface"
+set_module_property DESCRIPTION "AXI ADXCVR Core"
 set_module_property VERSION 1.0
 set_module_property GROUP "Analog Devices"
 set_module_property DISPLAY_NAME axi_adxcvr
+set_module_property ELABORATION_CALLBACK p_axi_adxcvr
 
 # files
 
@@ -27,10 +28,16 @@ set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
 add_parameter TX_OR_RX_N INTEGER 0
-set_parameter_property DEVICE_TYPE DISPLAY_NAME TX_OR_RX_N
+set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
-set_parameter_property DEVICE_TYPE TYPE INTEGER
+set_parameter_property TX_OR_RX_N TYPE INTEGER
-set_parameter_property DEVICE_TYPE UNITS None
+set_parameter_property TX_OR_RX_N UNITS None
-set_parameter_property DEVICE_TYPE HDL_PARAMETER true
+set_parameter_property TX_OR_RX_N HDL_PARAMETER true
+
+add_parameter NUM_OF_LANES INTEGER 4
+set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
+set_parameter_property NUM_OF_LANES TYPE INTEGER
+set_parameter_property NUM_OF_LANES UNITS None
+set_parameter_property NUM_OF_LANES HDL_PARAMETER true
 
 # axi4 slave interface
 
@@ -66,12 +73,27 @@ add_interface_port s_axi s_axi_rready rready Input 1
 
 # xcvr interface
 
-add_interface if_xcvr conduit end
+ad_alt_intf reset up_rst output 1 s_axi_clock
-add_interface_port if_xcvr up_rst             up_rst            Output   1
+set_interface_property if_up_rst associatedResetSinks s_axi_reset
-add_interface_port if_xcvr up_ref_pll_locked  up_ref_pll_locked Input    1
-add_interface_port if_xcvr up_pll_locked      up_pll_locked     Input    1
-add_interface_port if_xcvr up_ready           up_ready          Input    1
 
-set_interface_property if_xcvr associatedClock s_axi_clock
+add_interface ref_pll_locked conduit end
+add_interface_port ref_pll_locked up_ref_pll_locked export Input 1
 
+# name changes
+
+proc p_axi_adxcvr {} {
+
+  set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
+  set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
+
+  if {$m_tx_or_rx_n == 1} {
+    add_interface ready conduit end
+    add_interface_port ready up_ready tx_ready input $m_num_of_lanes
+  }
+
+  if {$m_tx_or_rx_n == 0} {
+    add_interface ready conduit end
+    add_interface_port ready up_ready rx_ready input $m_num_of_lanes
+  }
+}
 

library/altera/axi_adxcvr/axi_adxcvr_up.v

@@ -43,8 +43,7 @@ module axi_adxcvr_up (
 
   output                        up_rst,
   input                         up_ref_pll_locked,
-  input           up_pll_locked,
+  input   [(NUM_OF_LANES-1):0]  up_ready,
-  input           up_ready,
 
   // bus interface
 
@@ -64,6 +63,7 @@ module axi_adxcvr_up (
   localparam  [31:0]  VERSION = 32'h00100161;
   parameter   integer ID = 0;
   parameter   integer TX_OR_RX_N = 0;
+  parameter   integer NUM_OF_LANES = 4;
 
   // internal registers
 
@@ -75,6 +75,11 @@ module axi_adxcvr_up (
   reg                           up_rreq_d = 'd0;
   reg     [31:0]                up_rdata_d = 'd0;
 
+  // internal signals
+
+  wire                          up_ready_s;
+  wire    [31:0]                up_status_32_s;
+
   // defaults
 
   assign up_wack = up_wreq_d;
@@ -105,6 +110,10 @@ module axi_adxcvr_up (
 
   assign up_rst = up_rst_cnt[3];
   assign up_status = up_status_int;
+  assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
+  assign up_status_32_s[31:(NUM_OF_LANES+1)] <= 'd0;
+  assign up_status_32_s[NUM_OF_LANES] <= up_ref_pll_locked;
+  assign up_status_32_s[(NUM_OF_LANES-1):0] <= up_ready;
 
   always @(negedge up_rstn or posedge up_clk) begin
     if (up_rstn == 0) begin
@@ -118,8 +127,7 @@ module axi_adxcvr_up (
       end
       if (up_resetn == 1'b0) begin
         up_status_int <= 1'b0;
-      end else if ((up_pll_locked == 1'b1) && (up_ready == 1'b1) &&
+      end else if (up_ready_s == 1'b1) begin
-        (up_ref_pll_locked == 1'b1)) begin
         up_status_int <= 1'b1;
       end
     end
@@ -143,7 +151,7 @@ module axi_adxcvr_up (
           10'h002: up_rdata_d <= up_scratch;
           10'h004: up_rdata_d <= {31'd0, up_resetn};
           10'h005: up_rdata_d <= {31'd0, up_status_int};
-          10'h006: up_rdata_d <= {29'd0, up_pll_locked, up_ref_pll_locked, up_ready};
+          10'h006: up_rdata_d <= up_status_32_s;
           default: up_rdata_d <= 32'd0;
         endcase
       end else begin