spi_engine_offload: Define constraints for CDC

main
Istvan Csomortani 2020-04-20 16:09:11 +01:00 committed by István Csomortáni
parent ff4ce95110
commit 5493274fb7
2 changed files with 34 additions and 0 deletions

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@ -0,0 +1,31 @@
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
<: if { $async_spi_clk } { :>
set_property ASYNC_REG TRUE \
[get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
[get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
set_false_path -quiet \
-to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
<: } :>

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@ -3,10 +3,13 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create spi_engine_offload
adi_ip_files spi_engine_offload [list \
"spi_engine_offload_constr.ttcl" \
"spi_engine_offload.v" \
]
adi_ip_properties_lite spi_engine_offload
adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"
# Remove all inferred interfaces
ipx::remove_all_bus_interface [ipx::current_core]