From 5493274fb78121ef6edd90b57c3ece9cab3e6901 Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 20 Apr 2020 16:09:11 +0100
Subject: [PATCH] spi_engine_offload: Define constraints for CDC

---
 .../spi_engine_offload_constr.ttcl            | 31 +++++++++++++++++++
 .../spi_engine_offload_ip.tcl                 |  3 ++
 2 files changed, 34 insertions(+)
 create mode 100644 library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl

diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl
new file mode 100644
index 000000000..340cf26db
--- /dev/null
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl
@@ -0,0 +1,31 @@
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :>
+
+<: if { $async_spi_clk } { :>
+
+set_property ASYNC_REG TRUE \
+  [get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
+  [get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
+
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+<: } :>
diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
index fa8ae5004..52d3c603f 100644
--- a/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
+++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
@@ -3,10 +3,13 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
 
 adi_ip_create spi_engine_offload
 adi_ip_files spi_engine_offload [list \
+  "spi_engine_offload_constr.ttcl" \
 	"spi_engine_offload.v" \
 ]
 
 adi_ip_properties_lite spi_engine_offload
+adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl"
+
 # Remove all inferred interfaces
 ipx::remove_all_bus_interface [ipx::current_core]