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fmcadc1: sdc updates

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Rejeesh Kutty 2015-06-25 04:25:39 -04:00
parent c0dd80ccee
commit 543e08b67a
2 changed files with 9 additions and 6 deletions
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5
projects/fmcjesdadc1/a5gt/system_constr.sdc
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@ -6,5 +6,8 @@ create_clock -period "8.000 ns" -name eth_rx_clk_125mhz [get_ports {eth_rx
derive_pll_clocks
derive_clock_uncertainty
set_clock_groups -exclusive \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-group [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}] \